For e.g.
initial
begin
generate
for(genvar i; i < 4; i++)
//Code
endgenerate
end //initial
I'm getting error using QuestaSim with the concept. "Near generate: syntax error, unexpected generate "
1 Answer
No. generate blocks are evaluated during elaboration time. While initial,always and other procedural blocks start at zero simulation time, that is, run-time. Referring to Systemverilog IEEE 1800-2012 :
Generate schemes are evaluated during elaboration of the design. Although generate schemes use syntax that is similar to behavioral statements, it is important to recognize that they do not execute at simulation time.
They are evaluated at elaboration time, and the result is determined before simulation begins. Therefore, all expressions in generate schemes shall be constant expressions, deterministic at elaboration time.
In Verilog, instantiating a module means adding extra hardware to the board.
This hardware must be added before simulation starts(i.e. at compile time). You can not add/remove hardware during run time. You can either conditionally instantiate a module or multiply instantiate it, but never at run time.
Refer generate block syntax error question for an idea about your error. Also, refer this question for generate and genvar understanding. Referring IEEE 1800-2012 Chapter 27 for more information.
EDIT:
To create and pass multiple interface instances, the total number of interface instances must be governed by some parameter or macro. You can use this parameter in for loop in generate block to create distinct instances and set each of them using different key as follows:
// Generate multiple instances of interface
genvar i;
generate
for(i=0;i<NUM_OF_INTERFACES;i++)
begin
// Generate clk with different period for each instance
always #(i+1) clk[i] = ~clk[i];
inter in(clk[i]); // Create multiple instances here
initial
begin
// Set each and every instance
uvm_config_db#(virtual inter)::set(null,"*",$sformatf("in_%0d",i),in);
end
end
endgenerate
A complete example is created at EDAPlayground Multiple Interface link. Creating multiple instances can be referred from this question.
2 Comments
MayurKubavat
Based on number of "Interface" modules generated using "generate", I want to set all "Virtual Interfaces" in uvm_config_db. But I'm not able to use loops, as to refer each interface instance created by "generate", variables cannot be used."
sharvil111
I have edited answer for multiple interface instance creation and passing using
uvm_config_db. Kindly refer the given link for example code.
generate, code or module instances?