Explain this syntax error in testbench file

Question

I'm trying to create a testbench file for the sequential circuit in Modelsim (Verilog). But, I'm getting the following syntax error.

** Error: (vlog-13069) /Assignment_2x2_tb.v(6): near "initial": syntax error, unexpected initial, expecting ';' or ','.

Here's my code

module seq_circuit1_tb;
reg x,clk;
wire q;
seq_circuit1 seqct(x, clk, Q0, Q1)
//Module to generate clock with period 10 time units
initial begin
  forever begin
  clk=0;
  #10
  clk=1;
  #10
  clk=0;
  end
end
initial begin
  x=0;
  #50
  x=0;
  #50
  x=1;
  #50
  x=1;
  #50
end
endmodule

Why am I getting this error?

MikeCAT · Accepted Answer · 2015-09-06 03:23:57Z

2

You need a semicolon (;) after the line seq_circuit1 seqct(x, clk, Q0, Q1).

answered Sep 6, 2015 at 3:23

MikeCAT

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2 Comments

Atinesh Singh Over a year ago

Getting new error near "end": syntax error, unexpected end. at Line 24 just before endmodule.

MikeCAT Over a year ago

#50 just before end seems to be invalid. Maybe you should add $finish; or something before the end

Prashant · Accepted Answer · 2015-09-07 08:59:54Z

0

The initial block cannot end with a delay. You need to have some statement after the last #50 as follows

initial begin
  x=0;
  #50
  x=0;
  #50
  x=1;
  #50
  x=1;
  #50 $finish;
end
endmodule

or

initial begin
  x=0;
  #50
  x=0;
  #50
  x=1;
  #50
  x=1;
  // last #50 removed
end
endmodule

answered Sep 7, 2015 at 8:59

Prashant

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