I'm trying to build a Verilog file that imports global definitions from a defines file so I can keep track of all my FPGA endpoints in one place. In the my_defines file I have a list of variables like so:
`define PipeA 8'hA1
I import this file into the main file top_module using `include "my_defines.v"
When I instantiate the variable inside my top_module file, I noticed that you have to use `PipeA as the variable name instead of PipeA. If I've already imported this, why do I need the `?
`include is a verilog syntax which directs a compiler to include contents of other files in compilation. It is very similar to #include in C.
`define defines a named text replacement (macro), similar to the #define in C.
So, `define PipeA 8'hA1 defines the macro named PipeA with 8'h1 as a context. To use it in a program you need to follow verilog rules and to use the '`' syntax, as here: `PipeA.
An example
assign myVar[7:0] = `PipeA;
The pre-processor will replace `PipeA with the text form its definition:
assign myVar[7:0] = 8'h1;
The above result will be parsed by verilog.
Macro definitions are concidered global. The definition interpretation happens before any verilog analysis and is ortogonal to the scoping rules. So, no matter whre you define the macro, in a scope or outside a scope, it will still be defined everywhere within a compilation unit.
Also, standard Verilog does not have any concept of import. System verilog does, but it has nothing to do with the above.
There's a big difference between `include and import. import is something only SystemVerilog allows. The use of `define is text substitution in a pre-processing step without understanding any Verilog syntax. `PipeA invokes a text substitution macro, it is not a variable name. There is no global namespace as far as Verilog is concerned.
SystemVerilog has a package you can define which is a namespace that can be imported into a module (or another package).
