Verilog: Re-assigning a variable in an always block

Question

I want to create a logic where I update the value of a register whenever there is a pulse. In this, I need to update the all the register bits (8) to 1 except for one variable bit (x in below snippet) which needs to be set to 0.

For this I have a simple logic in place but I am not sure if this is synthesizable. I have not run lint yet.

always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    mask <= 8'b1;
  end
  else begin
    if (pulse) begin
      mask[7:0] <= 8'hFF;
      mask[x] <= 1'b0;
    end
    else
      mask[7:0] <= mask[7:0];
  end
end

Is this the best way to do it. I don't think so. Please suggest what should be the right way to do it.

what is x in mask[x]? Try to simulate first.

Serge
– Serge

2021-07-15 10:53:53 +00:00
Commented Jul 15, 2021 at 10:53 — Serge
– Serge, Commented Jul 15, 2021 at 10:53
X is a variable as I have explained in the description.

Shashank Shekhar
– Shashank Shekhar

2021-07-15 20:55:51 +00:00
Commented Jul 15, 2021 at 20:55 — Shashank Shekhar
– Shashank Shekhar, Commented Jul 15, 2021 at 20:55

dave_59 · Accepted Answer · 2021-07-15 17:01:19Z

2

Yes, you can make multiple assignments to the same variable (whole or a select of the variable) in the same always block. The last assignment wins.

Also, you should remove the mask[7:0] <= mask[7:0]; statement. It is unnecessary any sequential always block retains the value of any unassigned variable. This dummy assignment can interfere with a testbench's attempt to override the behavior for debugging or error injection.

answered Jul 15, 2021 at 17:01

dave_59

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2 Comments

ToTamire Over a year ago

This works also for <= assignments? I thought that this work only for = assignments.

dave_59 Over a year ago

It works for both when they are in the same procedural block. See the section on Determinism in the LRM. Section 4.6 in the IEEE 1800-2017 SystemVerilog LRM

user3307122 · Accepted Answer · 2021-07-16 08:05:34Z

-1

looks good, as mentioned you can remove:

else mask[7:0] <= mask[7:0];

you might consider also adding synchronized reset in a form of "kill" or something so you wouldn't have to use the a-synchronized reset "resetn"

answered Jul 16, 2021 at 8:05

user3307122

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