Questions tagged [fpga]
The fpga tag has no summary.
21 questions
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DE1-SOC 5CSEMA5F31 isn't detected in Quartus Program Device
I'm having trouble programming my DE1-SoC from the Quartus Programmer. The board is powered and connected correctly and I've managed to find and program it before, multiple times, but even then ...
- 11
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61
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U-Boot Not Booting from Flash Memory on Arty A7 100T FPGA
I'm working on booting U-Boot from the SPI flash memory of an Arty A7 100T FPGA and encountering an issue where U-Boot does not execute after power-on
Issue
U-Boot does not produce any output on the ...
- 101
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50
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What is needed to enable RPMsg IPC on SoC
I am working with an Intel SoC with a Hard Processor System (HPS), an Arm 64 core, and an FPGA fabric with a Nios soft processor. I would like to implement message passing between these two processors ...
- 11
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93
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Linux clock source from FPGA
I'm trying to get the Linux kernel (and system as a whole) to sync to a monotonically incrementing clock from a FPGA register in memory. The clock is 64-bits wide and divided into two 32-bit sections: ...
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1
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318
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Failing to install cvxpy.py on Ubuntu 22.04.3 LTS, on Zynq UltraScale+ MPSoC based SOM ARM Cortex-A53 4 core processor
I was barely able after much effort to get this to install 9 or so months ago, now it doesn't install on the same platform with a new update/upgrade. Here's the software version info:
ubuntu@BDv4-...
- 11
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1
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258
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Why does linux freezes when trying to access peripherals connected to the lightweight hps-to-fpga bridge (or any bridge)?
I have been working on a Altera DE1-SoC Development Board for 8 months. The system I was working on includes a Cyclone V FPGA chip, particularly the 5CSEMA5F31C6N. It was running an embedded Linux ...
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51
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Is it possible to partially virtualize the physical address space?
I'm currently working on systems that include FPGAs. We've various IP cores that support the AXI-Bus. To communicate with the IP cores of PL (programable logic), we need to map them onto the address ...
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125
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Frame buffer driver(altfb) not working with a 24 bit display
I am developing an embedded Linux system with a 24 bit LCD display. I use terasic linux-socfpga to compile the kernel and I want to use the altfb driver to show the desktop in LCD. For that, I copied ...
- 195
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209
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PCI-Express device refuses to wake up from D3
I’m working with a fpga expansion card (pci-e connected; terasic de10 pro).
My problem is whenever I don’t use the card for a couple of minutes it stops completely and only a complete shutdown can ...
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697
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How to Load Device Tree From Separate File in U-Boot Image
I'd like to load the device tree from a separate dtb file. So in the end I'd like to end up with the following files on my boot partition:
BOOT.BIN (first stage boot loader)
image.ub (U-Boot second ...
- 345
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2k
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Bus error when access nonaligned memory on zynq
EDIT: Is there a better stackexchange site I should put this on?
I am trying use the DDR4 connected to the FPGA side of a zynq ultrascale chip, specifically on Xilinx's devboard zcu102. I am using ...
- 154
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1
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2k
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Allow partial memory mapping of /dev/mem
I have a SoC-FPGA(DE0-nano-soc) which contains an ARM-Cortex-A9 cpu with a Cyclone V FPGA on a single chip. the CPU has access to 1gb of DDR3 memory but the FPGA can also access this memory so they ...
- 347
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374
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Share aarch64 page tables created by Linux with SMMU [closed]
I am currently working on creating a shared virtual address space in Linux arm64 on a Xilinx Zynq Ultrascale+ board. In the future it should be possible to share pointers/addresses between the Cortex ...
- 19
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213
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Changing Master Boot Record (MBR) starting partition address of boot loader
From what I understand, the partitioning of the Linux system - when booting from an SD card on an embedded device should look something similar to:
I want to move partition 2 up and merge it with the ...
- 11
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1
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3k
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Linux freezes when accessing io memory on an Xilinx ARM SoC
I am trying to read FPGA memory on a Xilinx Zynq board (zc702) as part of porting an RTEMS driver to Linux. I am using the devmem2 and mmap_test programs that I cross-compile for the board using the ...
- 201
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What is the difference between board level and Soc level information in DTS(device tree source) and DTSI?
For Device Tree Blob it says several boards can use one SoC so the SoC level information is included in board level in order not to be duplicated(DTSI is included in DTS). So
1.What is considered to ...
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1
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515
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How to enable USB with linux-socfpga?
I use linux-socfpga from Altera's github repository (the master branch which is recently updated) with my DE2-115 FPGA. The output from jtag configuration is:
$ jtagconfig1) USB-Blaster [2-2]
...
- 4,377
5
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1
answer
6k
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Linux Userspace PCI driver options? (uio_pci_generic)
I have a Xilinx FPGA PCIe end-point on the PCI Bus.
Linux picks up the device just fine and everything in lspci looks perfect.
My question is about PCI access options from user-space and what would ...
- 251
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2k
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How to Connect Internet in Zedboard using Linux via SDCard
I am working on Zedboard Zynq 7020. I have booted the Linux via SD card through Zedboard. The linux display can be shown onto the monitor via VGA cable. But I cannot connect that linux to internet. ...
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274
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Why u-boot starts so late after I give power
Running PetaLinux from sd card on ARM cortex A9 based Zynq zc702 board. Zynq is an SoC with ARM and FPGA.
Before the log messages (corresponding to U-Boot) starts printing, the screen (serial ...
- 1,732
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1
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910
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Any built-in Linux methods for AXI-burst type devices? [closed]
I need to communicate with an FPGA device based on an AXI-burst interface. What are the ways to access such a device through Linux without involving a DMA? Burst is an intrinsic property of the AXI ...
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