I need to perform basic operations on strings like concatenation,replacement and comparison in my Verilog simulation. How could it be possible? Is there any built-in support?
Thanks in advance.
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3 Answers
There is no string datatype in Verilog however verilog does support string literals and using them as byte vectors. This is the example from the spec:
module string_test;
reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display ("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display ("%s is stored as %h", stringvar,stringvar);
end
endmodule
Since strings use the reg datatype you can use the normal operators to manipulate them, keeping in mind each character uses 8 bits.
5.2.3.1 String operations
The common string operations copy, concatenate, and compare are supported by Verilog HDL operators. Copy is provided by simple assignment. Concatenation is provided by the concatenation operator. Comparison is provided by the equality operators. When manipulating string values in vector regs, the regs should be at least 8*n bits (where n is the number of ASCII characters) in order to preserve the 8-bit ASCII code.
You'll have to write some tasks or functions if you need operations like searching.
Comments
If you have access to a modern simulator which supports SystemVerilog syntax, there is a string data type. Strings can be concatenated and compared. Refer to the IEEE Std (1800-2009).
Comments
sjtaheri,
Reviving a dead thread, but I see this question come up, and there is a newer solution for it.
svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more. This project was presented at DVCon 2014.
