Can I find the execution time of verilog code?

Question

I know that verilog is an HDL and its all about parallel processing but the problem I face is that I have to write a report on why a section of C++ code is better in an HDL environment.

So I have the C++ code, which I wrote in Verilog. It works perfectly. Now I have to write a report on how this section of code is faster in Verilog. So I have to do execution time comparisons.

I managed to find the execution time of my C++ code using the following method:

#include <iostream.h>
#include <time.h>
using namespace std;


int main()
{
    clock_t t1,t2;
    t1=clock();
    //code goes here
    t2=clock();
    float diff ((float)t2-(float)t1);
    cout<<diff<<endl;
    system ("pause");
    return 0;

}

Now how can I get the same result in Verilog? Is there any option in the Xilinx compiler that can tell me how long this code will take to produce the end result after it has been programmed onto an FPGA board? or can I add something to the code that will be able to give this result?

Thank you

This code is not written in Verilog, this is not Verilog syntax, probably you wrote this and cross compiled it for Xilinx Linux... You can not synthesize such code... — joy
– joy, Commented Oct 22, 2013 at 20:29
The code I gave is in C++. It's just an example. The actual code is very long. What I wanted to say is that the <time.h> is the method I used to find out the execution time in C++. — StuckInPhDNoMore
– StuckInPhDNoMore, Commented Oct 22, 2013 at 20:36
On an fpga, or verilog simulator it is going to take a number of clock cycles to compute the result. multiply this by 1/clock_frequency and you have the execution time. — Morgan
– Morgan, Commented Oct 22, 2013 at 21:10

user1619508 · Accepted Answer · 2013-10-22 22:30:07Z

5

I think you are missing the point entirely. You don't execute programs in Verilog, you design hardware with it. It's a hardware description language. Running a simulation of your Verilog and using the $time or $realtime commands will tell you nothing about how long it actually takes for your algorithm to run in hardware.

What you need to do is synthesize your Verilog to an FPGA, then look at the synthesis reports to see how long it will take from a change in the algorithm inputs until the output(s) are valid. Of course, you may need to add pipelining or use synthesis constraints to get a decent result from synthesis. This is not a trivial process, so expect to spend time learning how it is done and done well.

answered Oct 22, 2013 at 22:30

user1619508

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2 Comments

EML Over a year ago

I agree that the OP has obviously missed the point of his homework, but I'll just point out that you do 'execute programs' in Verilog. It is, and always has been, a simulation language. turning a Verilog description into hardware is a difficult problem which is solved with heuristics, and by using only a subset of the language.

user1619508 Over a year ago

@EML In this case the OP specifically asked about execution time "after it has been programmed into an FPGA", and I would argue that running a simulation in Verilog is still vastly different from writing a program in Verilog. I apologize if my tone was harsh, but I am exhausted by students who treat Verilog and VHDL as though they were simply another programming language.

DOS · Accepted Answer · 2013-10-22 21:26:50Z

1

I think what you are looking for is this: $time

Here is a quick example: http://www.asic-world.com/verilog/vbehave2.html example

answered Oct 22, 2013 at 21:26

DOS

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1 Comment

Morgan Over a year ago

I would always use $realtime, then your not limited by your time accuracy.

Serge · Accepted Answer · 2017-06-18 17:53:34Z

Verilog is about describing behavior of hardware. A verilog simulator is to simulate the description on a computer. A verilog emulator is to emulate the behavior implementation in fpgas.

In any case the simulation or emulation take multiple cycles. Your C++ program takes only '1' cycle. So, first of all you have to make it to run for multiple cycles, providing change in clocks. Something like this:

for (int i = 0; i < MAX_CYCLES; i++) {
    myClk = ~ myClk;
    executeMyCode(myClk);
}

for verilog simulations you would need something like that to toggle clocks:

initial begin
    for (int i = 0; i < MAX_CYCLES; i++) begin
        #1 myClk= ~myClk
    end
    $finish;
end

you cannot synthesize the above in fpgas, so for emulation you would need to play with clocks and tell the emulator for how long to run (MAX_CYCLES?), make sure that the clock changes as many times as in c++ or simulation.

verilog simulation does never run in parallel on a computer. It just pretends to do so by altering evaluation order of different parts of the model.

Emulation does real parallelism based on the hardware implementation.

Depending on the nature of the code you might find that c++ is better :-).

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