Verilog Input to Wire

Question

I am trying to make a clock in Verilog on my Altera DE2 board. As of now, I can count from 00:00:00 to 23:59:59 using flipflops as a clock. Now I need to be able to set Switches to some value, say 12:56:00 then have it count up from there. I am trying to set a wire variable to be the initial switches input then use that as a starting point for my counter.

module part3(HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,SW,KEY,LEDR,CLOCK_50);

input [17:0] LEDR, SW;
input [3:0] KEY;
input CLOCK_50;
output [0:6] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;

parameter clock_speed = 50000000;
parameter clock_divisor = 8;

wire [26:0] Q,Q2,Q3,Q4;
wire [3:0] one,two,three,four;
reg SecInc,MinInc,HrInc;
    
one = SW[3:0];

This is my code up to where it crashes. I do not understand why

   wire in = SW[0];

is legal but assigning it the way I have done it not legal. I need to store the switch input in a register or a wire so I can increment that register or wire based on a condition.

Note: I have no formal intro to Verilog, our prof gave us a board and a link to the altera university program labs and said have fun.

toolic · Accepted Answer · 2013-11-15 16:33:56Z

3

You need to use the assign keyword. Change:

one = SW[3:0];

to:

assign one = SW[3:0];

That is known as a continuous assignment in Verilog. You don't need the assign keyword if you are making a procedural assignment (inside an always block, for example).

answered Nov 15, 2013 at 16:33

toolic

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