Systemverilog assignment - logic array to byte array

Question

I'm trying to assignment logic l_data[31:0]; to byte data[];.

data = l_data; is not legal SystemVerilog assignment. How can it be done?

data is 8 bits l_data is 32 bits wide. Which bits of l_data do you want to assign to data? — Morgan
– Morgan, Commented Jan 1, 2014 at 20:26

Greg · Accepted Answer · 2014-02-22 01:53:37Z

5

Use a bit-stream cast (section 6.24.3 of the IEEE Std 1800-2012 LRM). You will need to create a typedef for the cast, but it is a good idea to use typedefs for all your variable declarations anyways.

typedef byte unsigned dynamic_byte_array_t[];
typedef logic fixed_logic_array_t[31:0];

dynamic_byte_array_t data;
fixed_logic_array_t l_data;

data = dynamic_byte_array_t'(l_data);

A couple of notes:

Be careful using byte, it is signed by default.
I add a _t suffix to all my type basic names,
I suggest using more meaningful type names than what I have used here.
The bit-stream cast has one specific order to move bits-left-to-right. Use the streaming operator if you need more complex bit ordering (Section 11.4.14)

edited Feb 22, 2014 at 1:53

Greg

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answered Jan 2, 2014 at 0:03

dave_59

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