Unresolved Reference Error in Verilog Module when trying to simulate

Question

When I try to simulate the following module via a testbench, I receive this error:

unresolved reference to 'if2to4'

Here is my code:

module h3to8(din, eout, en);

  //Port Assignments
  input [2:0] din;
  input [0:0] en;
  output reg [7:0] eout;

  //3-to-8 decoder

  always @(din)
    begin 
  
      eout = 8'b00000000;
      if(din[2] == 1'b0)
        if2to4 half1 (din[1:0], eout[3:0], en);
      else
        if2to4 half2 (din[1:0], eout[7:4], en);
      
    end

endmodule

module if2to4 (in, out, en);

  //Port Assignments
  input [1:0] in;
  input [0:0] en;
  output reg [3:0] out;

  //2-to-4 decoder
  always @(in)
    begin
  
    if(en == 0)
      out = 4'b0000;
    
    else
     if(in == 0)
       out = 1;
     else if(in == 1)
       out = 2;
     else if(in == 2)
       out = 4;
     else
       out = 8;
        
    end

endmodule

The verilog code is designed to implement a 3-to-8 decoder using two 2-to-4 decoders. I thought I instantiated the modules correctly, but I keep receiving an unresolved reference error in regard to module if2to4. The code compiles without error, and this particular error only occurs when trying to run a simulation.

toolic · Accepted Answer · 2020-09-23 17:56:09Z

2

You can not instantiate modules inside an always block like that. Try this:

module h3to8(din, eout, en);

  //Port Assignments
  input [2:0] din;
  input [0:0] en;
  output reg [7:0] eout;

  //3-to-8 decoder

    if2to4 half1 (din[1:0], eout[3:0], en);
    if2to4 half2 (din[1:0], eout[7:4], en);

endmodule

Or, you can use din[2] as part of the enable:

module h3to8(din, eout, en);

  //Port Assignments
  input [2:0] din;
  input [0:0] en;
  output reg [7:0] eout;

  //3-to-8 decoder

    if2to4 half1 (din[1:0], eout[3:0], en&~din[2]);
    if2to4 half2 (din[1:0], eout[7:4], en&din[2]);

endmodule

edited Sep 23, 2020 at 17:56

answered Mar 5, 2014 at 0:49

toolic

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