how to declare output array in verilog?

Question

I am trying to ADD two array and want output in array in verilog code. But error is occured. which is ERROR:HDLCompiler:1335: Port sum must not be declared to be an array in verilog code . can anyone tell me how to declare output array in verilog code. Thanks.

module array(clk,sum,reset);
            input clk,reset;
            //input [7:0] din;
            //input [7:0] A[3:0]; 
            //input [7:0] B[3:0];  
            output  sum[3:0];
            wire [7:0] sum[3:0];
            reg [7:0] A[3:0]; 
            reg [7:0] B[3:0];
            integer i;
            always@(posedge clk)
            begin 
                if(reset==1'b1)
                    begin
                    A[0]<=1;
                    A[1]<=2;
                    A[2]<=3;
                    A[3]<=4;
                    B[0]<=5;
                    B[1]<=5;
                    B[2]<=5;
                    B[3]<=5;
                    sum[0]<=0;                  
                   sum[1]<=0;   
                    sum[2]<=0;  
                    sum[3]<=0;  
                    end 
                else 
                    begin   
                        for(i=0;i<4;i=i+1)
                            begin 
                                sum[i]=(A[i] + B[i]);
                            end 
                 end 
               end 
   endmodule

Community · Accepted Answer · 2017-05-23 11:52:43Z

3

Array style ports are only supported in SystemVerilog, if you can use that you should probably stop using the Verilog-95 style port declaration.

Verilog 2001 and above port declaration, with SystemVerilog multi dimension ports

module array(
  input             clk,
  input             reset,
  input       [7:0] A  [3:0],
  input       [7:0] B  [3:0], 
  output reg  [7:0] sum[3:0]
);

Verilog vs SystemVerilog files are often identified by file extension so saving as a .sv file will normally switch the compiler over to SystemVerilog.

A combinatorial version on EDA Playground using the free modelsim 10.1d simulator.

Also note that if you are assigning a value to sum in an always block it needs to be a reg not a wire. Since your using SystemVerilog now everything can be declared as logic instead, for more info Checkout this answer.

edited May 23, 2017 at 11:52

CommunityBot

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answered Nov 17, 2014 at 12:05

Morgan

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2 Comments

Raviraj Over a year ago

Thank you for giving me reply. But I am not using systemVerilog, I am using verilog. And I used module input and output as you mentioned, but it gave me more error in verilog code. Please, give me another option in verilog code.

Morgan Over a year ago

@Raviraj Verilog-1995, Verilog-2001 and Verilo-2005 do not support Array style ports, The syntax was added in 2009 and from on then is known as SystemVerilog. This is not the same as the per-2009 SystemVerilog which was a verification add-on to Verilog. Today they are the same thing. Most free simulators have varying levels of support for SystemVerilog. So unless your tool constrained or under strict guidelines to stick to a specific Verilog standard you should be able to move to SystemVerilog.

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