Verilog simple register testbench

Question

I want to infer a simple flip flop using verilog. Here is the code.

module tb_simpleRegister();

  reg clk;
  reg a;
  wire b;

  simpleRegister dut
  (
    .clk(clk),
    .a(a),
    .b(b),
    .c(c)
  );


  initial begin
    clk=1;
    a=0;
    #10
    a=1;
    #10
    a=0;
  end

  always #5 clk = ~clk;
endmodule

module simpleRegister(
    input clk,
    input a,
    output reg b,
    output reg c
    );

    always @(posedge clk) begin
        b <= a;
        c <= b;
    end
endmodule

And here is the result when I run it. The b output of dut does not behave like a flip flop. However output c does. Any comments on why is this happening?

What do you mean with "does not behave like a flip flop"? What is the intended result? — mcleod_ideafix
– mcleod_ideafix, Commented Apr 12, 2015 at 6:26

Morgan · Accepted Answer · 2015-04-12 10:32:58Z

4

I would rewrite the test bench as follows:

initial begin
    @(posedge clk);
    a<=0;
    @(posedge clk);
    a<=1;
    @(posedge clk);
    a<=0;
  end

//Clock in separate process
initial begin
  clk=1;
  forever begin
    #5 clk = ~clk;
  end
end

The non-blocking assignment will ensure the value of a is changed just after the clock edge giving the testbench a full cycle setup.

answered Apr 12, 2015 at 10:32

Morgan

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1 Comment

Jane Lexmark Over a year ago

Thanks. Your code works fine. Also when I change my initial loop to "initial begin clk=1; a<=0; #10 a<=1; #10 a<=0; end" it works.

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