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Hi this code is supposed to represent NOR and NAND gate in HDL my benchtest gives not outputs but compiles, I dont know what the problem is.Thanks in advance

   module ipriority_encoder_gates(output x,y,V,input D0,D1,D2,D3);//V2001
   wire w1,D2_not;
   not (D2_not,D2);
   or  (x,D2,D3);
   or  (V,D0,D1,x);
   and (w1,D2_not,D1);
   or  (y,D3,w1);
   endmodule

   /* Benchtest begins here */
   module priority_encoder_beh(output reg X,Y,V,input D0,D1,D2,D3);
   always @ (D0,D1,D2,D3)begin
   X=0;
   Y=0;
   V=0;
   casex ({D0,D1,D2,D3})
    4'b0000: {X,Y,V}=3'bxx0;
    4'b1000: {X,Y,V}=3'b001;
    4'bxx10: {X,Y,V}=3'b011;
    4'bxx10: {X,Y,V}=3'b101;
    4'bxxx1: {X,Y,V}=3'b111;
    default: {X,Y,V}=3'b000;
    endcase
    end
    endmodule

    module t_priority_encoder_beh();
    wire X,Y,V;
    reg D0,D1,D2,D3;
    integer k;

    priority_encoder_beh M0(X,Y,V,D0,D1,D2,D3);

    initial #200 $finish;
    initial begin
    k=32'bx;
    #10 for(k=0;k<= 16;k=k+1) #10{D0,D1,D2,D3}= k;
    end
    endmodule
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1 Answer 1

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If you are running a Verilog simulator such as NCVerilog, VCS, etc., then you probably won't be seeing any output because your code doesn't contain, e.g., any $display statements or $monitor statements.

For instance, you might try replacing:

initial begin
    k=32'bx;
    #10 for(k=0;k<= 16;k=k+1) #10{D0,D1,D2,D3}= k;
end

With something like:

initial begin
    k=32'bx;
    #10 for(k=0;k<= 16;k=k+1)
    begin
       #10{D0,D1,D2,D3}= k;
       $display("D=%b, X=%b, Y=%b, V=%b", {D0,D1,D2,D3}, X, Y, V);
    end
end
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