Adding and Subtracting values in Verilog

Question

I am writing a program that acts as a cash deposit box. Everything occurs on the clock edge. If enable is true and reset is true, the value in the box resets to 0. If enable is true and add is 1, we add the amount to the box. If enable is true and add is 0 we subtract from the box.

Here is my code and test bench

module cashbox(output [15:0] value, input [15:0] amount, input add,enable, clock, reset);
reg value;

 always @(posedge clock)
 begin
if(enable) begin
  if(reset)begin
    value <= 0;
    end
  else begin
    if(add)begin
     value <= value + amount;
     end
    else begin
      value <= value - amount;
      end
    end

end    

end
endmodule

// cashbox testbench

module cashbox_tb;
reg [15:0] amt;
reg add, en, clk, rst;
wire [15:0] value;

cashbox cb(value, amt, add, en, clk, rst);

always
    #50 clk = ~clk;

initial begin
    $display("Amount in box %d", value);
    clk = 1; en = 1; add = 1;
    rst = 1; #10 rst = 0;
     amt = 100; add = 1;
    #170 en = 1; #100 en = 0;  // 90
    #20 amt = 50; add = 0;
    #180 en = 1; #100 en = 0;  // 290
    #20 amt = 75; add = 1;
    #180 en = 1; #100 en = 0;  // 490
    #20 amt = 35; add = 0;
    #180 en = 1; #100 en = 0;  // 690
    #20 amt = 50; add = 0;
    #180 en = 1; #100 en = 0;
    #810 $finish;
end
endmodule

Everything compiles but when I run it, it displays Amount in box X. It doesnt display a value

I changed my test bench to this // cashbox testbench

module cashbox_tb;
reg [15:0] amt;
reg add, en, clk, rst;
wire [15:0] value;

cashbox cb(value, amt, add, en, clk, rst);

always
    #50 clk = ~clk;

initial begin
   $monitor("Amount in box %d",value);
    clk = 0; en = 0; add = 0;
    rst = 1; #10 rst = 0;
    #10 amt = 100; add = 1;
    #170 en = 1; #100 en = 0;  // 90
    #20 amt = 50; add = 0;
    #180 en = 1; #100 en = 0;  // 290
    #20 amt = 75; add = 1;
    #180 en = 1; #100 en = 0;  // 490
    #20 amt = 35; add = 0;
    #180 en = 1; #100 en = 0;  // 690
    #20 amt = 50; add = 0;
    #180 en = 1; #100 en = 0;
    #810 $finish;
end
endmodule

And now my output is back to saying Amount in box X

I'm using an online compiler on tutorialspoint.com

user3370950
– user3370950

2015-04-15 18:45:10 +00:00
Commented Apr 15, 2015 at 18:45 — user3370950
– user3370950, Commented Apr 15, 2015 at 18:45

toolic · Accepted Answer · 2025-03-31 11:44:53Z

2

$display is only executed at time 0. Change that to $monitor so that you get a display message every time value changes:

$monitor("Amount in box %d", value);

Here is the output I get with VCS:

Amount in box     0
Amount in box     1
Amount in box     0

Refer to IEEE Std 1800-2012, section "21.2.3 Continuous monitoring".

I get compile warnings with VCS, and I get a compile error with Incisive.

This can be cleaned up by changing:

module cashbox(output [15:0] value, input [15:0] amount, input add,enable, clock, reset);
reg value;

to:

module cashbox(output reg [15:0] value, input [15:0] amount, input add,enable, clock, reset);

After that change, here is my output:

Amount in box     0
Amount in box   100
Amount in box   200
Amount in box   150
Amount in box   225
Amount in box   190
Amount in box   140

edited Mar 31 at 11:44

answered Apr 15, 2015 at 18:33

toolic

62.9k21 gold badges81 silver badges130 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Adding and Subtracting values in Verilog

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related