I ran into this line in a SystemVerilog sim, I've googled around but I'm not sure what it's doing:
data_w = { >> 32 { { >> { data } } } };
Any clarification would be much appreciated! Thanks!
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1 Answer
It is called streaming. It exists in SystemVerilog; not Verilog. For a full explanation, refer to IEEE Std 1800-2012 § 11.4.14 Streaming operators (pack/unpack)
The slice_size determines the size of each block, measured in bits. If a slice_size is not specified, the default is 1. If specified, it may be a constant integral expression or a simple type. If a type is used, the block size shall be the number of bits in that type. If a constant integral expression is used, it shall be an error for the value of the expression to be zero or negative.
The stream_operator<<or>>determines the order in which blocks of data are streamed:>>causes blocks of data to be streamed in left-to-right order, while<<causes blocks of data to be streamed in right-to-left order. Left-to-right streaming using>>shall cause the slice_size to be ignored and no re-ordering performed. Right-to-left streaming using<<shall reverse the order of blocks in the stream, preserving the order of bits within each block. For right-to-left streaming using<<, the stream is sliced into blocks with the specified number of bits, starting with the right-most bit. If as a result of slicing the last (left-most) block has fewer bits than the block size, the last block has the size of the remaining bits; there is no padding or truncation.
Examples form IEEE Std 1800-2012 § 11.4.14.2 Re-ordering of the generic stream
int j = { "A", "B", "C", "D" }; { >> {j}} // generates stream "A" "B" "C" "D" { << byte {j}} // generates stream "D" "C" "B" "A" (little endian) { << 16 {j}} // generates stream "C" "D" "A" "B" { << { 8'b0011_0101 }} // generates stream 'b1010_1100 (bit reverse) { << 4 { 6'b11_0101 }} // generates stream 'b0101_11 { >> 4 { 6'b11_0101 }} // generates stream 'b1101_01 (same) { << 2 { { << { 4'b1101 }} }} // generates stream 'b1110