syntax error in verilog code ,near "<=": syntax error, unexpected <=,

Question

I am beginner in verilog so I need your help please. I wanted to make a code for 2 digit 7 segments decoder but there is a syntax here that I can't recognize it.

The code:

module segment7dec (input [5:0] bin,output [3:0] bcd0,output [3:0] bcd1);


  case (bin)
 6'd0 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0000; end

 6'd1 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0001; end

 6'd2 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0010; end

 6'd3 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0011; end

 6'd4 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0100; end

 6'd5 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0101; end

 6'd6 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0110; end

 6'd7 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0111; end

 6'd8 : begin bcd1 <= 4'b0000; bcd0 <= 4'b1000; end

 6'd9 : begin bcd1 <= 4'b0000; bcd0 <= 4'b1001; end

6'd10 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0000; end

6'd11 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0001; end

6'd12 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0010; end

6'd13 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0011; end

6'd14 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0100; end

6'd15 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0101; end

6'd16 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0110; end

6'd17 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0111; end

6'd18 : begin bcd1 <= 4'b0001; bcd0 <= 4'b1000; end

6'd19 : begin bcd1 <= 4'b0001; bcd0 <= 4'b1001; end

6'd20 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0000; end

6'd21 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0001; end

6'd22 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0010; end

6'd23 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0011; end

6'd24 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0100; end

6'd25 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0101; end

6'd26 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0110; end

6'd27 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0111; end

6'd28 : begin bcd1 <= 4'b0010; bcd0 <= 4'b1000; end

6'd29 : begin bcd1 <= 4'b0010; bcd0 <= 4'b1001; end

6'd30 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0000; end

6'd31 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0001; end

6'd32 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0010; end

6'd33 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0011; end

6'd34 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0100; end

6'd35 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0101; end

6'd36 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0110; end

6'd37 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0111; end

6'd38 : begin bcd1 <= 4'b0011; bcd0 <= 4'b1000; end

6'd39 : begin bcd1 <= 4'b0011; bcd0 <= 4'b1001; end

6'd40 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0000; end

6'd41 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0001; end

6'd42 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0010; end

6'd43 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0011; end

6'd44 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0100; end

6'd45 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0101; end

6'd46 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0110; end

6'd47 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0111; end

6'd48 : begin bcd1 <= 4'b0100; bcd0 <= 4'b1000; end

6'd49 : begin bcd1 <= 4'b0100; bcd0 <= 4'b1001; end

6'd50 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0000; end

6'd51 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0001; end

6'd52 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0010; end

6'd53 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0011; end

6'd54 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0100; end

6'd55 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0101; end

6'd56 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0110; end

6'd57 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0111; end

6'd58 : begin bcd1 <= 4'b0101; bcd0 <= 4'b1000; end

6'd59 : begin bcd1 <= 4'b0101; bcd0 <= 4'b1001; end

6'd60 : begin bcd1 <= 4'b0110; bcd0 <= 4'b0000; end
endcase
  endmodule

The reported error:

Error: C:/modeltech64_10.1c/examples/decoder1.v(4): near "<=": syntax error, unexpected <=, expecting IDENTIFIER or TYPE_IDENTIFIER

stackoverflow.com/help/how-to-ask , stackoverflow.com/help/no-one-answers you may need to read this things before post .. Please edit and Increase the Post Quality to not get flagged — Prasad
– Prasad, Commented Mar 2, 2016 at 7:20
Use case in some procedural statement. Like initial, always blocks etc. — sharvil111
– sharvil111, Commented Mar 2, 2016 at 7:21

Morgan · Accepted Answer · 2016-03-02 08:49:02Z

3

Two main issues, assignents can be made using assign to wires or delcare as reg and place in an initial or always block. For example:

module segment7dec (
  input  [5:0] bin,
  output reg [3:0] bcd0,  //<-- reg type
  output reg [3:0] bcd1);

bcd driven by flip-flops:

 always @(posedge clk) begin
   case (bin)
     6'd0 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0000; end
     6'd1 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0001; end
     //...
   endcase
 end

Or for combinatorial (note the change in assignment type):

 always @* begin
   case (bin)
     6'd0 : begin bcd1 = 4'b0000; bcd0 = 4'b0000; end
     6'd1 : begin bcd1 = 4'b0000; bcd0 = 4'b0001; end
     //...
   endcase
 end

answered Mar 2, 2016 at 8:49

Morgan

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2 Comments

Matthew Over a year ago

While you were typing your answer, I was typing my near identical answer. Except I didn't spot the non-blocking assignments for combinational logic. I spend too much time doing VHDL.

Mahmoud Alaa Over a year ago

Morgan,Matthew , I understand the errors now , they seem to me very silly now after I got it :D , thanks very much for your response.

Matthew · Accepted Answer · 2016-03-02 09:27:12Z

There are two problems preventing you compiling this:

i) The case statement must be within an always block. Any similar statement (eg if) must be in an always block. If the concept of an always block is not familiar to you, you do need to find out about them.

always @(*)
case (bin)

ii) By default, outputs are wires. You cannot drive a wire from an always block. You can only assign to a reg from an always block. Your outputs both need to be a reg.

module segment7dec (input [5:0] bin, output reg [3:0] bcd0, output reg [3:0] bcd1);

Your assignments in the always block should also be "blocking", as this is combinational logic:

6'd0 : begin bcd1 = 4'b0000; bcd0 = 4'b0000; end

http://www.edaplayground.com/x/RxS

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