Verilog if statement assign error

Question

I'm trying to learn verilog having done C++ before. As a learning exercise I'm trying to flash turn an LED on after seeing 10 button presses. I also have an additional reset button that starts the 10 count again. What ever I try I can't get it to compile. Can anyone point me in the right direction?

My code is:

module led_counter (button, nreset, led);

input button, nreset; 
output led;
reg counter[4:0];           // to hold the current count

always @ (negedge nreset) begin
    counter <= 0;           // Just reset counter
end

always @ (negedge button) begin

    if (counter == 10) begin // see if the button has been pressed 10 times
        led_state <= 1;      // turn the led on
    end

    else begin 
    led_state <= 0;          // the led is off
    counter <= counter + 1; 
    end

end

assign led = led_state;

endmodule

Krouitch · Accepted Answer · 2016-03-07 10:41:52Z

3

led_state is not declared, it should be a reg.

To have something more concise I would also regroup the two processes into one. It would make it look like a synchronous process with asynchronous reset, i.e. triggered by a clock and reseted on falling edge of a reset.

always @ (posedge button or negedge nreset) begin
    if(~nreset)       //reset counter when nreset is low
        counter <= 0;
    else begin        //do something on posedge of button
      //Do something//
end //end process

It would also be more likely to be synthesized.

answered Mar 7, 2016 at 10:41

Krouitch

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1 Comment

Martin Over a year ago

Thanks for the comment @krouitch - that helped. I don't think this is quite what I'm looking for as the nreset input is actually a latching button instead of a momentry button. So i really just wanted to detect edges. I believe with the nreset button latched low this code would always be resetting the counter even when the posedge of the button triggered it. Can it be modified to meet these new requirements?

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