Here's some simple code for defining 2-dimensional array of wires in Verilog.
module test(a, b, c);
input [63:0] a;
input [63:0] b;
output [63:0] c [63:0];
endmodule
When I compile the code, I get this error.
Illegal reference to net array "c".
I don't think this question https://stackoverflow.com/questions/3011510/... helps with this specific problem.
You get this error, because it is illegal in Verilog (pre-2009 when it merged into SystemVerilog) to have ports that are two (or more) dimensional arrays; for arrays on ports, only simple, one-dimensional vectors are allowed.
You can have two (or more) dimensional arrays of nets or variables, as this question does explain https://stackoverflow.com/questions/3011510/....
It's worth noting that there is no such a restriction in System-Verilog (or: Multi-dimensional arrays are allowed.
Although Verilog doesn't allow defining 2- or more- dimensional arrays of nets, there is a nice workaround using 'generate' statement. You can generate a set of wires then address them using a particular iteration. Here is an example:
module Example (
input[7:0] in,
output[7:0] out
);
generate
genvar i;
for (i=0; i<=7; i=i+1) begin: stage
wire[7:0] net;
if (i!=0) assign net = stage[i-1].net;
end
endgenerate
assign stage[0].net = in;
assign out = stage[7].net;
endmodule
In this example an 8*8 array of wires is created, they connected sequentially using specifier of previous iteration, after that the first and the last iterations are connected to input and output of module.
In the similar manner you can create 3 and more dimensional array.
