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I have a std_logic_vector, x: std_logice_vector(A+B-1 downto 0), and I want to set the top A bits to '1' and the bottom B bits to '0', is there an easy way to do this?

I would like to do something like this:

x <= (A+B-1 downto B <= (others => '1'),
        B-1 downto 0 <= (others => '0'));

My other plans are to define the sub signals and join them:

signal top: std_logic_vector(A-1 downto 0);
signal bottom: std_logic_vector(B-1 downto 0);
...
top <= (others => '0');
bottom <= (others => '1');
x <= top & bottom;

Or I could write a function that loops over all the bits but that seems like a lot of work for something this easy.

If there isn't an easy way and since I need to do this multiple times I might define a constant and use that.

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  • 4
    x <= (A+B-1 downto B => '1') & (B-1 downto 0 => '0'); Commented Apr 19, 2016 at 12:04
  • That works, thank you. I'd not seen the => used apart from when setting others. Commented Apr 19, 2016 at 12:11
  • Then read about "named association", there's a lot of uses for it. Commented Apr 19, 2016 at 12:13

1 Answer 1

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Another option is to use aliases. For example:

architecture test of foo is
  signal x: std_logic_vector(A+B-1 downto 0);
  alias x_upper is x(A+B-1 downto B);
  alias x_lower is x(B-1 downto 0);
begin
  x_upper <= (others => '1');
  x_lower <= (others => '0');
end architecture test;

You can treat the aliases just like signals. (And they are fully synthesizable).

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2 Comments

That's really interesting, I've been making a lot of extra signals to do this kind of thing. I guess most of the time the wiring would work out the same but it's nice to be explicit. Thank you.
@R.Mckemey Exactly why I like aliases. When you use an intermediate signal, the slicing distant from the declaration. Using aliases, the slicing is right next to the signal declaration, so it is very clear and explicit what the signal is meant to do.

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