I have a std_logic_vector, x: std_logice_vector(A+B-1 downto 0), and I want to set the top A bits to '1' and the bottom B bits to '0', is there an easy way to do this?
I would like to do something like this:
x <= (A+B-1 downto B <= (others => '1'),
B-1 downto 0 <= (others => '0'));
My other plans are to define the sub signals and join them:
signal top: std_logic_vector(A-1 downto 0);
signal bottom: std_logic_vector(B-1 downto 0);
...
top <= (others => '0');
bottom <= (others => '1');
x <= top & bottom;
Or I could write a function that loops over all the bits but that seems like a lot of work for something this easy.
If there isn't an easy way and since I need to do this multiple times I might define a constant and use that.
=>used apart from when setting others.