Clocking Issue in FPGA with MATLAB HDL Coder

First of all, i do not understand why you would upsample by 32 and then 4 times by 2. You should analyze the slowest path.

If the addition is a bottleneck, that would be in the 32x upsampling and 8,8,8 would be better. However, all depends on the implementation, which I can't guess from here.

I would advise to have a look at FIR filters. Reducing the number of FIR stages will increase your speed at the cost of increased , SNR, which may or may not be tolerable. You could take one with a very short impulse response.

You could also reduce the number bits used to represent the samples. This will again decrease the SNR but consume less logic and is likely to be faster.

You also consider to or not to use hard multiplier blocks, if available in the technology you are targetting.

Otherwise, have a look at parallel FIR filter implementations. Though I bet you'll have to implement that one yourself.

And of course, as you pointed out yourself, realistic constraints are required.

Good luck. Please consider liking my post.

Thank for the answer. Yes i need the 4 stages of upsampling because of my project requirements. My input sampling frequency is varying and my output should always be 11.2 MHz, so thats why i need those 4 different stages in order to generate output for 4 different stages.

I optimized the FIR filters by using pipeline registers, reduced the number of multipliers of the 32 upsample one using the partly serial architecture.

I guess the problem was i was not using a SDC file as need for timinig analysis by altera, now when i configure a simple SDC file, i get positive slack value and a restriected Fmax of 24.5 MHz, as my output needs to be 11.2 MHz i guess this is fine enough.

If you have some more suggestions on this please let me know, i did not quite understand the fact of the SNR