I have following line in my VHDL code:
prbs_reg_feed <= prbs_reg_ip(byte_indx);
where
type reg_type is array (0 to 63) of std_logic_vector(8 downto 0);
signal prbs_reg_feed : std_logic_vector(8 downto 0);
signal prbs_reg_ip : reg_type;
I want know the FPGA implementation of this.
Thanks, Vijay
With care, and some knowledge of your target FPGA, this will be implemented as a memory block instead of combinational logic.
A typical restriction is that the assignment
prbs_reg_feed <= prbs_reg_ip(byte_indx);
has to be placed in a clocked process, as the memory blocks are typically synchronous.
The only way to be sure is to take a few minutes and try synthesising this block on its own, and read the synthesis report. And if it doesn't work first try, read the documentation and experiment further.
Some examples here for RAM. ROM can be the same, but without any way to write it, and perhaps declaring prbs_reg_ip as a constant instead of a signal, for example
constant prbs_reg_ip : reg_type := ( 0 => X"C3", 1 => "80", 2 => "FF", ...);
For some FPGAs or FPGA tools, you may need to add an attribute to the signal (or type) representing the memory, for example
signal prbs_reg_ip : reg_type;
attribute ram_style : string;
attribute ram_style of prbs_reg_ip : signal is "block"; -- or "distributed"
See this Xilinx answer for an example of this.
This will get synthesised to a lot of combinational logic. This combinational logic will have nearly 600 inputs and 9 outputs.
With an FPGA synthesier, if you were to write some code around this line:
prbs_reg_feed <= prbs_reg_ip(byte_indx);
to make your code behave more like a RAM, then you would probably get a RAM. (You should read the report files output by your synthesiser to make sure.)
process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
prbs_reg_ip(byte_indx) <= datain;
end if;
prbs_reg_feed <= prbs_reg_ip(byte_indx);
end if;
end process;
NB: this assumes byte_indx is an integer.