two's complement binary VHDL

Intuitively my reasoning would be: you are using two's complement, which is a signed number representation, therefore negative values exist. If negative values exist, you need a sign bit. That will leave 7-bits for the magnitude: hence you can only represent a value between -128 and 127. Value 251 is not within this range: It cannot be represented using 8-bits two's complement notation. Thus only -5 is valid.

The easiest way to realize two's complement sign inversion in VHDL is using the numeric_bit package.

library ieee;
entity bit_inv is
    generic(width : positive);
    port(
        A     : in  bit_vector(width-1 downto 0);
        A_inv : out bit_vector(width-1 downto 0));
end entity;

architecture rtl of bit_inv is
    use ieee.numeric_bit.all;
begin
    A_inv <= bit_vector(-signed(A));
end architecture;

entity bit_inv_tb is end entity;

library ieee;
architecture beh of bit_inv_tb is
    use ieee.numeric_bit.all;
    constant width : positive := 8;
    signal A, A_inv : bit_vector(width-1 downto 0);
begin
    DUT : entity work.bit_inv
        generic map(width => width)
        port map(A=>A, A_inv =>A_inv);

    test: process begin
        A <= bit_vector(to_signed(5,width));
        wait for 1 ns;
        assert to_integer(signed(A_inv)) = -5 report "A_inv is not equal to -5" severity failure;
        wait;
    end process;
end architecture;