SystemVerilog: convert two 1D array into 2D array

Question

logic [7:0] a;
logic [7:0] b;
logic [1:0][7:0] c;
assign c = {{a},{b}};

If I had a and b, how could I convert it into type of c? I guess one obvious way is to use:

assign c[0] = a;
assign c[1] = b;

But imagine c was not a logic variable, but a input port of a module.

mymodule inst_mymodule (
    .c_i({{a},{b}}) // c is logic [1:0][7:0]
    .o(out)
);

what would you do?

dave_59 · Accepted Answer · 2018-07-07 05:55:33Z

1

Since you are using packed arrays, it does not matter what the type of c is. It just needs to be 16 bits. Also you don’t need the extra {}’s around a and b. You can write {a,b}

answered Jul 7, 2018 at 5:55

dave_59

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2 Comments

user849204 Over a year ago

Isn't the type of {a,b} same as logic [15:0]?

dave_59 Over a year ago

Yes it is the same as logic [15:0] which is assignment compatible with logic [1:0][7:0]

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