Accessing register values in verilog

Question

I initialize a register

reg[1:0] yreg;

and manipulate it a bit, i.e., value from prev. iteration of program is shifted to 1 spot when I add in the new value in the 0 spot

yreg = SIGNAL; //here SIGNAL is an input to the program

And then I want to access the values at the 0 and 1 spots in the register later for a calculation. How can I do this? My initial reaction was yreg[0] and yreg[1] (I normally program in python =) but this is producing an error (line 35 is the line of code that has yreg[0] and yreg[1] in it):

ERROR:HDLCompiler:806 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 35: Syntax error near "[".

My assumption when I saw this was that it's not the right syntax to use the brackets to access a certain index of the register. How do you properly access the information in an index of a register? I'm having trouble finding information on this.

Sorry for the probably ridiculous question, this is my first time ever using verilog or FPGAs in general.

Full Code

module trapverilog(
    input CLK,
    input SIGNAL,
     input x,
    output OUT
    );

reg[1:0] yreg;
float sum = 0;

always @(posedge CLK)
begin
    yreg = SIGNAL; //should shift automatically...?
    sum = ((reg[0] + reg[1])*x/2) + sum; //this is effectively trapezoidal integration
    OUT = sum;
end

endmodule

Can you give more details on your code and the error syndrome? — kevin1494
– kevin1494, Commented Jul 31, 2018 at 3:14
I would love to help but the question is unclear, consider rewriting to describe the error and what do you want to achieve and what you've done so far. — RaZ
– RaZ, Commented Jul 31, 2018 at 13:27

user149341 · Accepted Answer · 2018-07-31 16:52:15Z

1

You have a fundamental misunderstanding of how Verilog signals work.

By default, all Verilog signals are single bits. For example, in your code, SIGNAL, x, and out are all one bit wide. They cannot store a number (other than 0 or 1).

Specifying a width when you define a signal (like reg [1:0] yreg) controls how many bits are used to represent that signal. For instance, yreg is a two-bit signal. This does not mean that it "shifts automatically"; it just means that the signal is two bits wide, allowing it to be used to represent numbers from 0 to 3 (among other things).

I would strongly advise that you work through a course in digital electronics design. Verilog programming is very different from procedural programming languages (such as Python), and you will have a hard time making sense of it without a solid understanding of what you are actually building here.

answered Jul 31, 2018 at 16:52

user149341

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2 Comments

auden Over a year ago

How can you make x and out longer than 1 bit?

user149341 Over a year ago

The same way as you'd make another signal into a bus: output [31:0] out. Or whatever.

auden · Accepted Answer · 2018-07-31 15:26:57Z

0

Apparently as per this answer using brackets to get a certain index of a register is correct. I just forgot to call the variable properly - I was calling reg[0] instead of yreg[0]. Changing this fixed the error.

answered Jul 31, 2018 at 15:26

auden

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