Make file header file dependency

Question

I want to add header file dependency in make file

I written rule

 ${OBJECTDIR}/%.o: %.cc %.h
 gcc  $(WarningLevel)  $(CFLAGS) $(INCLUDES)  -c  -o $@  $^

but there are two error

One for .cc file which don't have any .h files . It will give no rule to make. Second one is the object file build by rule give error at linking

file format not recognized; treating as linker script

how can I achieve that ? (source file should be compile if header file is got modified )

Generally, you turn translational units into object files, and since header files and not standalone translational units, it seems odd that you list %.h as a dependency to begin with. — J T
– J T, Commented Mar 22, 2011 at 16:10
I think there is no simple solution here. Even $(wildcard %.h) will not work since functions are expanded before matching (I got bitten by this several times). You could 1) use something based on $(shell find ...), define, $(foreach) and $(eval) but this is tricky, 2) use gcc's -M option family to generate dependencies for you. I usually go for the second one but I'm at work and I don't have an example right now for you. — Alexandre C.
– Alexandre C., Commented Mar 22, 2011 at 16:12
The make file is tab sensitive. The gcc line should be \tgcc <STUFF> ie a tab character in-front of gcc. — Loki Astari
– Loki Astari, Commented Mar 22, 2011 at 17:04
For your information, the way to generate dependency automatically is shown here Automatic Prerequisites. This might be helpful for you. — Ise Wisteria
– Ise Wisteria, Commented Mar 22, 2011 at 20:31

Jack Kelly · Accepted Answer · 2011-03-22 20:02:43Z

2

First of all, you haven't shown us your link command. Secondly, you shouldn't be using $^ here. $^ expands to a list of all dependencies (here, the .c and the .h), but we only want to compile the .c file. Use $<, which expands only to the name of the first dependency:

${OBJECTDIR}/%.o: %.c %.h
        gcc $(WarningLevel) $(CFLAGS) $(INCLUDES) -c -o $@ $<

answered Mar 22, 2011 at 20:02

Jack Kelly

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Comments

J T · Accepted Answer · 2011-03-22 16:14:07Z

1

You need to provide a rule for the header file dependency you listed:

%.h:
    echo This is my build target for header files.

Make won't actually do anything with the %.h files, but atleast you're telling it to watch for file changes (which then cause the .o files to need recompilation).

answered Mar 22, 2011 at 16:14

community wiki

J T

3 Comments

Alexandre C. Over a year ago

If no file is produced, this will not work. Either add touch $^ as a recipe (which will create an empty file), or try to use .PHONY:%.h which shouldn't be good either.

Chris Dodd Over a year ago

This is right answer for the .cc file without a .h file (though it is a bit of a hack). The linking error is coming from the link command, which the OP doesn't show, so there's no way we can say what is wrong with that.

Vivek Goel Over a year ago

@chris linking error is for each .o file which is build using rule ${OBJECTDIR}/%.o: %.cc %.h gcc $(WarningLevel) $(CFLAGS) $(INCLUDES) -c -o $@ $

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