Problem outputting solution for a 2 digit BCD adder using Verilog

Question

I am building a 2 digit BCD adder using only one module. I am rather new to verilog so i don't know if i made a mistake with some of the assignments, but the simulation wont output any answer it just give me the X error for my output. I dont know if i made a mistake in coding the module or coding the simulation but all the waveform output shows is the inputs but give me no outputs. I just want to know where i went wrong. I am kinda stuck here.

I am trying to create this:

The code for module is as follows:

   `timescale 1ns / 1ps


module two_digit_BCDAdder(input [7:0] X, input Load, input clk, output [8:0]R );

reg [7:0] Q=0;
always @(posedge clk)
begin 
if (Load)
Q<=X;
else 
Q<=Q;
end 
// 8 bit register 

wire sum1, sum3; 

//wires for both upper  parallel adders sum1 left adder sum 3 right adder

 wire cout1, cout2, cout3, cout4;
// wires for cout,  being cout1 top left adder, cout 2 bottom left adder,
//  cout3 top right adder, cout 4 bottom right adder

 wire cin;
// wire for or gate connected to cin

 wire d1,d2;
// D1 connects or gate of the comparator and cout 1 to PA bottom left,
//  D2 connects or gate of the comparator and cout 1 to PA bottom right,

 wire C1,C2;
// C1 comparator on the left 
// C2 comparator on the right

 assign cin = (cout1|cout2);
// Cin or gate

 assign d1 = (cout1|C1);
 assign d2 =(cout3|C2);
// Creation of or gates

 assign C1 = (sum1 > 4'b1001);
 assign C2= (sum3 > 4'b1001);
// Comparator sum hase tobe greater than 9 for BCD addition

 assign {cout3, sum3}= {Q[0],Q[1],Q[2],Q[3]}+{X[0],X[1],X[2],X[3]};
// Top right Parallel Adder
 assign {cout4,{R[0],R[1],R[2],R[3]}} = sum3+{1'b0,d2,d2,1'b0};
// Bottom left Comparator

 assign {cout1,sum1} = {Q[4],Q[5],Q[6],Q[7]}+{X[4],X[5],X[6],X[7]}+cin;
 // Top left Parallel Adder

 assign {cout2,{R[4],R[5],R[6],R[7]}} = sum1 +{1'b0,d1,d1,1'b0};
 // bottom left Parallel Adder

 assign R[8]=(d1|cout2); 
//or gate for final carry led

endmodule

This is the simulation code i am working with:

    `timescale 1ns / 1ps

module BCD_sim();
reg [7:0]x;
reg b;
reg clk;
wire[8:0]r;

two_digit_BCDAdder uut(x,b,clk,r);

initial
begin 
clk =0;

 forever #1 clk=~clk;
end


initial
 begin 

x=0; b=0;
//Values for test
#2 x=55; b=1;
#2 x=55; b=0;
#4;
#2 x=99; b=1;
#2 x=99; b=0;
#4;
#2 x=87; b=1;
#2 x=78; b=0;
#4;
#2 x=25; b=1;
#2 x=75; b=0;
#4;
#2 x=33; b=1;
#2 x=66; b=0;
#4;
#2 x=69; b=1;
#2 x=96; b=0;



$finish;
end 
endmodule

Rama Krishna Meda · Accepted Answer · 2020-02-20 09:11:24Z

I have updated the code to make it modular.. and picture with inked modular names is added

     `timescale 1ns / 1ps

module two_digit_BCDAdder(
    input           clk,
    input [7:0]     X,
    input           Load,
    output [8:0]    R
);

reg [7:0] Q = 0;

// 8 bit register
always @(posedge clk)begin
    if (Load) Q <= #10 X;
    else      Q <= #10 Q;
 end

 wire [3:0] AM,AL,BL,BM;
 wire [3:0] sum_PA1,sum_PA2,sum_PA3,sum_PA4;
 wire       cin_PA1,cin_PA2,cin_PA3,cin_PA4;
 wire       cout_PA1,cout_PA2,cout_PA3,cout_PA4;
 wire       or_gate1_out,or_gate2_out,or_gate3_out,or_gate4_out;
 wire       c1_ag9,c2_ag9;

 assign AL = Q[3:0] ;
 assign AM = Q[7:4] ;
 assign BL = X[3:0] ;
 assign BM = X[7:4] ;

adder PA1(
    .a     (AM)
   ,.b     (BM)
   ,.c_in  (or_gate3_out)
   ,.sum   (sum_PA1)
   ,.c_out (cout_PA1)
);

adder PA2(
    .a     (AL)
   ,.b     (BL)
   ,.c_in  (1'b0)
   ,.sum   (sum_PA2)
   ,.c_out (cout_PA2)
);

adder PA3(
    .a     ({1'b0,{2{or_gate1_out}},1'b0})
   ,.b     (sum_PA1)
   ,.c_in  (1'b0)
   ,.sum   (sum_PA3)
   ,.c_out (cout_PA3)
);

adder PA4(
    .a     ({1'b0,{2{or_gate4_out}},1'b0})
   ,.b     (sum_PA2)
   ,.c_in  (1'b0)
   ,.sum   (sum_PA4)
   ,.c_out (cout_PA4)
);

comp C1(
    .a   (sum_PA1)
   ,.ag9 (c1_ag9)
);

comp C2(
    .a   (sum_PA2)
   ,.ag9 (c2_ag9)
);

or_gate or_gate1 (
  .a   (cout_PA1)
 ,.b   (c1_ag9)
 ,.out (or_gate1_out)
);

or_gate or_gate2 (
  .a   (or_gate1_out)
 ,.b   (cout_PA3)
 ,.out (or_gate2_out)
);

or_gate or_gate3 (
  .a   (cout_PA2)
 ,.b   (cout_PA4)
 ,.out (or_gate3_out)
);

or_gate or_gate4 (
  .a   (c2_ag9)
 ,.b   (cout_PA2)
 ,.out (or_gate4_out)
);

 assign R[3:0]  = sum_PA4;
 assign R[7:4]  = sum_PA3;
 assign R[8]    = or_gate2_out;

endmodule

 module adder (input  [3:0] a,b,
               input        c_in,
               output [3:0] sum,
               output       c_out
);
    assign {c_out,sum} = a+b+c_in;
endmodule

module comp (input [3:0] a,
             output      ag9
);
   assign ag9 = a > 4'h9;
endmodule

module or_gate(input  a,b,
               output out
);
    assign out = a||b;
endmodule

and new tb file with named port connections to dut

     `timescale 1ns / 1ps

module BCD_sim();
reg [7:0]x;
reg b;
reg clk;
wire[8:0]r;

two_digit_BCDAdder dut(
     .clk    (clk)  
    ,.X      (x)
    ,.Load   (b)   
    ,.R      (r)
);

initial
begin 
clk =0;
 forever #1 clk=~clk;
end


initial
 begin 

x=0; b=0;
//Values for test
#2 x=55; b=1;
#2 x=55; b=0;
#4;
#2 x=99; b=1;
#2 x=99; b=0;
#4;
#2 x=87; b=1;
#2 x=78; b=0;
#4;
#2 x=25; b=1;
#2 x=75; b=0;
#4;
#2 x=33; b=1;
#2 x=66; b=0;
#4;
#2 x=69; b=1;
#2 x=96; b=0;



$finish;
end 
endmodule

with the above files vivdo simulator is showing the results..

simple code instead of modular

    module two_digit_BCDAdder(
    input           clk,
    input [7:0]     X,
    input           Load,
    output [8:0]    R
);

reg [7:0] Q = 0;

// 8 bit register
always @(posedge clk)begin
    if (Load) Q <= #10 X;
    else      Q <= #10 Q;
 end

 wire [3:0] AM,AL,BL,BM;
 wire [3:0] sum_PA1,sum_PA2,sum_PA3,sum_PA4;
 wire       cin_PA1,cin_PA2,cin_PA3,cin_PA4;
 wire       cout_PA1,cout_PA2,cout_PA3,cout_PA4;
 wire       or_gate1_out,or_gate2_out,or_gate3_out,or_gate4_out;
 wire       c1_ag9,c2_ag9;

 assign AL = Q[3:0] ;
 assign AM = Q[7:4] ;
 assign BL = X[3:0] ;
 assign BM = X[7:4] ;

 //4 Adders
 assign {cout_PA1,sum_PA1} = AM[3:0] + BM[3:0] + or_gate3_out;
 assign {cout_PA2,sum_PA2} = AL[3:0] + BL[3:0] + 1'b0        ;
 assign {cout_PA3,sum_PA3} = sum_PA1[3:0] + {1'b0,{2{or_gate1_out}},1'b0} + 1'b0;
 assign {cout_PA4,sum_PA4} = sum_PA2[3:0] + {1'b0,{2{or_gate4_out}},1'b0} + 1'b0;

 // 2 Comparators
 assign c1_ag9 = sum_PA1 > 4'h9 ;
 assign c2_ag9 = sum_PA2 > 4'h9 ;

// 4 OR gates
assign or_gate1_out = cout_PA1     || c1_ag9   ;
assign or_gate2_out = or_gate1_out || cout_PA3 ;
assign or_gate3_out = cout_PA2     || cout_PA4 ;
assign or_gate4_out = cout_PA2     || c2_ag9   ;

// Assigning outputs
 assign R[3:0]  = sum_PA4;
 assign R[7:4]  = sum_PA3;
 assign R[8]    = or_gate2_out;

endmodule

Would it be possible to reduce the number of modules to contain it within one module or is that something that is not possible. Like instead of making a PA adder or a comparater module is there a way to reduces that. Or is that not a thing that can be done.
In the vivado simulator(2019.2) and vcs (version O-2018.09-SP2-1) i tried this code i am able to see the toggling of the cout_*
Rama, what was the main problem with the code i provided? Was it the or gate declaration or the assignment? Was comparing to the simplified code and those see to be the most glaring but it seems that something more as the fixes i made still give me a truncated answer.

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