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I'm trying to generate a vhdl code using the HDL code generator in Matlab. I have a matlab function and its test bench. This is the matlab function: function [received_signal_real, ...
user25608955's user avatar
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1 answer
231 views

My question is quite basic to most appropriate levels on consideration. I lack the perception of how can I dump or implement my matlab code on a hardware component like processors or fpga? For eg: ...
Sukshith Shetty's user avatar
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1 answer
423 views

I have coded an algorithm using MATLAB R2019 script and i want it to be called in an System verilog file i.e The output generated by the matlab script is actually to be fed into the testbench ...
Ansuman Mishra's user avatar
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1 answer
251 views

I want to use HDL coder to convert MATLAB xcorr function to VHDL language. My code is given in below, i think i made a mistake when I'm defining the input data types. What should be the input data ...
Mehmet Şerefoğlu's user avatar
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1 answer
963 views

I have an HDLC frame like blow and I want to calculate the HCS and FCS algorithm. Its based on DLMS protocol noted in green book page 128. Here is an example of this frame: Ex.1: Frame=`(...
Pitter's user avatar
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1 vote
0 answers
262 views

Currently I am trying to follow the MathWorks tutorial 1 to register a TE0720 with a TE0701-6 carrier board in Matlab. I followed the instructions, designed the block design and exported it as advised....
fukurai's user avatar
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1 vote
0 answers
105 views

I am trying to program a module in Matlab that will be translated to Verilog. My module has a lot of inputs, so I want to group them into a unique string of bits so the module will have only one input....
Rodrigo Serna Pérez's user avatar
1 vote
0 answers
185 views

I am trying to perform cosimulation in HDL Coder using ModelSim 10.2c .But getting below error : Failed Cannot connect to 'Mentor Graphics ModelSim' HDL simulator Does any one know what could be ...
Haider's user avatar
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-3 votes
1 answer
1k views

I have a system in Simulink/HDL coder (see below image please). I have 3 outputs and 3 inputs. I want my system to run 10 times. After each iteration it should select the outputs and use them as ...
jutt veer's user avatar
0 votes
1 answer
754 views

I am sorry If I say some thing silly.Please forgive me: I am trying to convert Matlab code(given below) to VHDL code,using HDL coder.It contains a function called sum.But when I try to convert the ...
Haider's user avatar
  • 13
3 votes
1 answer
90 views

I have 4 buttons on an FPGA dev board so I wrote function [HEX0] = Bar(KEY) n = uint8(sum(KEY, 'native')); ... Unfortunately, HDL Coder turned it into the following chunk of VHDL: y := '0'; FOR ...
Dmitri Nesteruk's user avatar