In ModelSim, the following code works just fine:
string r;
string s;
// ...assign some string to s...
integer i;
r = "";
for (i=s.len()-1; i>=0; i=i-1) begin
if (s[i] != "\n") begin
r = {s[i], r};
end
end
In Aldec Riviera, this causes a compilation error Incompatible types at assignment: .r<string> <- s[i]<byte>.
Reading the SystemVerilog LRM, I can see that the curly braces seem to be only supported to concatenate strings, not bytes. So either ModelSim is not as strict with the LRM or it implicitly converts the s[i] byte to a one-character string (which seems sensible in this context). In Riviera, it looks like I have to convert the byte s[i] to a one-character string manually. What is the most efficient and concise solution (if possible without having to introduce a temporary variable)?
s[i]to be treated as a string of length 1, not abyte. It seems to me that Riviera may not be doing the right thing. Do you have an LRM reference related to this? Also, curly braces can certainly be used to concatenate bits/logic/bytes - this is a hold over from Verilog and may not be explicit in the SystemVerilog LRM.stringor a string literal. Of course, concatenation of bits, logic and bytes using {} is ok too, but the result wouldn't be a string then.