My current project involves an address counter entity that outputs a 7-bit vector and that output (m) goes into a sine lookup table entity. So basically, I want m to be the x, and the output of the sine entity to be the y. But my issue lies in the entries for the lookup table. How do I turn the actual real values into std_logic_vectors?
For example, an entry's sine is 34.1326. How does that turn into a vector?
Although baldyHDL's answer will work, you can now use the (now-standard and synthesisable) fixed-point types to save a lot of manual effort.
You can choose how many bits you want to the left and right of the binary point. There are functions to directly convert reals into fixed point.
You can find the library at http://www.vhdl.org/fphdl/
For example:
signal a : sfixed (7 downto -6);
This has 7 bits to left of point (for a range of -64 to +63) and 6 bits to the right of the point, each is worth 2^-6 = 0.015625.
Then you can do:
s <= to_sfixed(34.1326);
and you will get the closest number that is representable in the form you requested. Given the resolution of your inputs, that's probably not close enough, so change the -6 to something more negative to get more resolution.
multiply your entries by a value 2^n and round the result. the result can be represented as a std_logic_vector, keeping in mind that this has "n" post-comma bits. choose "n" in a way, that the quantisation after rounding is adequate!
example:
caution: choose your vector size carefully and be aware of SIGNS
