How to add std_logic using numeric_std

Question

Using numeric_std and vhdl93, I cant seems to figure out how to add a std_logic signal to a std_logic_vector.

library ieee;
use ieee.numeric_std.all;

signal in_a, out1: std_logic_vector(3 downto 0);
signal s1 : std_logic;

out1 <= std_logic_vector(signed(in_a) + s1);

Unless you are required to use std_logic_vector, it is much preferable to use signed or unsigned directly, especially for signals, but also for ports. This avoids the need for casts everywhere, and helps document what signals are used for. Positive numeric values (counters, addresses): unsigned. Positive or negative numeric values (data): signed. Non-numeric data (control signals, aggregates): std_logic(_vector). — zennehoy
– zennehoy, Commented Sep 9, 2013 at 11:16

user1155120 · Accepted Answer · 2013-09-08 23:38:42Z

6

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_std_logic is
end entity;

architecture foo of add_std_logic is
   signal in_a, out1: std_logic_vector(3 downto 0);
   signal s1 : std_logic;
   signal s1v:  std_logic_vector(0 to 0);
begin

    s1v <= (others => s1);

    out1 <= std_logic_vector(signed(in_a) + signed(s1v));

end architecture;

architecture fum of add_std_logic is
   signal in_a, out1: std_logic_vector(3 downto 0);
   signal s1 : std_logic;
   subtype s1v is  std_logic_vector(0 to 0);
begin

    out1 <= std_logic_vector(signed(in_a) + ( s1 & ""));

end architecture;

And of course you could move in_a, s1 and out1 to the port.

answered Sep 8, 2013 at 23:38

user1155120

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1 Comment

spiderplant0 Over a year ago

Thanks: I see the trick is to create a vector of length 1: ( s1 & "")

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