How to form the variable name using defines in system verilog, actually i need to configure my registers (around 100). to do that i need to hardcode the 100 statement. is there any way to form a variable using define(anyother way)?
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3 Answers
A typical use of Defines (or tick defines).
Define
`define HIER2 testbench_top.hier1.hier2
Usage
initial begin
if( `HIER2.sub_component.wire == 1'b1)
However
SystemVerilog IEEE 1800-2012 Section 22.5.1 `define, covers text macros which can take arguments.
`define DISPLAY_MACRO1(a=1,b="A",c) $display(a,,b,,c);
`DISPLAY_MACRO1(4,5,6);
// Expands to $display(4,,5,,6)
Arguments can be skipped to allow the default:
`DISPLAY_MACRO1( ,5,6);
// Expands to $display(1,,5,,6)
The macros can also be used to create equations
`define TOP(a,b) a + b
a = `TOP(g ,h)
// expanding to
// a = g + h
This is not directly useful for creating variable names because it requires spaces to delimit arguments, this is where the `` come in handy. They are used to delimit without using a space.
`define MAKE_REG( width, name) reg [ width -1:0] name``_register
`MAKE_REG( 4, enable) ;
//should expand to
// reg [ 4 -1:0] enable_register ;
Comments
The way to form an identifier in a `define is by using `` which joins tokens together into a single token
`define CONCAT(A, B) A``B
int `COCNCAT(X, Y); // defines an **int** XY
Sometimes you will see
`define myreg(name) \
int _reg_``name;
So `myreg(0) declares _reg_0
There is no looping macro construct in SystemVerilog, so if you need _reg_0, _reg_1, ... you are better off declaring an array or using a generate statement.
Comments
define myreg(name) \
int _reg_``name;
So myreg(0) declares _reg_0
There is no looping macro construct in SystemVerilog, so if you need _reg_0, _reg_1, ... you are better off declaring an array or using a generate statement.
In the above statement,
please give clarification on how to use generate statement/array for req_0,req_1...
