using assign statement for `define statement

Question

I am using assign statement of verilog for assigning `define as below in my driver module.

`define  SPI_MASTER_P_IF spi_vif.spi_master_p.spi_master_p_cb

`define SPI_MASTER_N_IF spi_vif.spi_master_n.spi_master_n_cb

`define SPI_MASTER_IF

class my_driver extends uvm_driver;

  assign `SPI_MASTER_IF = (if_posedge)?`SPI_MASTER_P_IF: `SPI_MASTER_N_IF;

endclass

When I compile I am facing the error as "near "assign": syntax error, unexpected assign, expecting function or task"

What is the proper way to do this assignment?

nguthrie · Accepted Answer · 2014-03-05 20:33:44Z

4

You cannot define a macro using an assign statement. What you want here is ifdef:

`ifdef IF_POSEDGE
  `define SPI_MASTER_IF SPI_MASTER_P_IF
`else
  `define SPI_MASTER_IF SPI_MASTER_N_IF
`endif

See section 22.6 of the 1800-2012 standard.

edited Mar 5, 2014 at 20:33

answered Mar 5, 2014 at 13:48

nguthrie

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Comments

Greg · Accepted Answer · 2014-03-05 18:21:01Z

3

The definition SPI_MASTER_IF is empty. The code becomes:

assign = (if_posedge)?spi_vif.spi_master_p.spi_master_p_cb:spi_vif.spi_master_n.spi_master_n_cb

which is illegal.

Also assign might not be used there too, please check the IEEE Std 1800-2012 section 8.3 (class syntax) in the specification.

edited Mar 5, 2014 at 18:21

Greg

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answered Mar 5, 2014 at 14:33

Sung-Yu Chen

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2 Comments

Greg Over a year ago

you are correct that assign cannot used in a class.

Sung-Yu Chen Over a year ago

If it is to choose the clocking block to do something at runtime, perhaps it's better to use fork...join, and use if([!]if_posedge) in each process to run or not to run.

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