Verilog generate statement issue

Question

I was trying to use the generate function in Verilog. The code compiled successfully, but it couldn't simulate. I get the following errors:

Illegal output or inout port connection for "port 'sum'".
Illegal output or inout port connection for "port 'carry'".

Could anyone tell me what am I doing wrong?

module test(input wire [2:0] a, 
        input wire [2:0] b,
        output reg [2:0] s,
        output reg [2:0] c);

genvar i;
generate 
for(i=0;i<3;i=i+1)
    adder_half inst(.sum(s[i]),.carry(c[i]),.a(a[i]),.b(b[i]));
endgenerate 

endmodule

module adder_half(
  output sum,carry,
  input a,b
    );
 xor(sum,a,b);
 and(carry,a,b);

endmodule

I didn't made one, I directly used the tool's( ModelSim) simulate option. — user3185902
– user3185902, Commented Mar 27, 2014 at 18:42
I changed my adder output type to reg, still I'm getting the same error. module adder_half( output reg sum,carry, input a,b ); always@(*) begin sum=a^b; carry=a&b; end endmodule — user3185902
– user3185902, Commented Mar 27, 2014 at 18:52
Sorry my fault, and thanks it started working, but am i not supposed to use reg type inside blocks (here its generate block) — user3185902
– user3185902, Commented Mar 27, 2014 at 19:00
The type is only relevant for current module. an output of reg is connected to wire at the next level of hierarchy. — Morgan
– Morgan, Commented Mar 27, 2014 at 20:10

toolic · Accepted Answer · 2014-03-27 19:06:44Z

3

The reg type is only used for procedural assignments, but instance connections are treated more like continuous assignments.

Remove the reg keyword from your outputs. Change:

    output reg [2:0] s,
    output reg [2:0] c);

to:

    output [2:0] s,
    output [2:0] c);

answered Mar 27, 2014 at 19:06

toolic

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