Error when trying to synthesize verilog code

Question

I am trying to make a module that performs the twos complement of a value if the msb is 1. It works in cadence, however when I try to synthesize it I get the following error:

Cannot test variable X_parallel because it was not in the event expression or with wrong polarity.

The code for the module is as follows:

module xTwosComp (X_parallel, Clk, Reset, X_pos);
input [13:0] X_parallel;
input Clk, Reset;
//wire X_msb; //was an attempt at fixing the problem
output [13:0] X_pos;
reg [13:0] X_pos;

//assign X_msb=X_parallel[13];//failled attempt at fixing

always @ (posedge Clk or posedge Reset)
begin
        if (X_parallel[13]) begin
             X_pos = ~(X_parallel) +1;
        end else begin
             X_pos = X_parallel;
        end
end

endmodule

Greg · Accepted Answer · 2014-12-07 00:36:44Z

2

You are missing your reset statement. Not sure if this fixes the exact error, but synthesizers expect code to determine what events are asynchronous when there is more than one edge event.

You need an if (Reset) begin X_pos <= 14'b0; else before the if (X_parallel[13]). Otherwise posedge Reset is treated as another clock and not a asynchronous reset. This will confuse the synthesizer.

FYI: flops should be assigned with non-blocking assignments (<=). It will save you from debugging false race condition and RTL to gates simulation mismatches.

answered Dec 7, 2014 at 0:36

Greg

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Comments

PatrickR · Accepted Answer · 2014-12-07 00:46:38Z

1

After countless hours I have figured it out. It was because i was not referencing Clk or Reset in my always block.

Thanks to anyone who considered the issue.

Thanks Greg for your answer, although I figured out how to make it work I am very glad for your response since it cleared up why it works now. Thanks!

answered Dec 7, 2014 at 0:46

PatrickR

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