Verilog compiler error

Question

    module router (clock, ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3, PacketIn0, PacketIn1, PacketIn2, PacketIn3, PacketOut0, PacketOut1, PacketOut2, PacketOut3);

   input   clock;
   input   ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3;  
   input [7:0] PacketIn0, PacketIn1, PacketIn2, PacketIn3;
   output [7:0] PacketOut0,PacketOut1, PacketOut2, PacketOut3;

   reg [3:0]   bvp, vp;
   reg [1:0]   counter0, counter1, counter2, counter3;
   reg [2:0]   sel0, sel1, sel2, sel3;
   reg [3:0]   zero=0;
   reg [7:0]   addr0, addr1, addr2, addr3, out0, out1, out2, out3l;
   wire        np0, np1, np2, np3;
   wire [7:0]  PacketOut0, PacketOut1, Packetout2, Packetout3;

   always@(posedge clock)
     bvp[0]<=ValidPacket0;
   if (ValidPacket0 && !bvp[0]) vp[0]=1'b1;
   else vp[0]=0;

The above code gives me the following error:

** Error: proj1a.v(23): near "[": syntax error, unexpected '[', expecting "IDENTIFIER" or "TYPE_IDENTIFIER" or '#' or '('
Line 23 is at the if statement.

Any Insight?

Community · Accepted Answer · 2017-05-23 10:34:44Z

1

Depending on what you're trying to do, you either need to add begin and end keywords around the statements after always @(posedge) (and fix your assignment type, see How to interpret blocking vs non blocking assignments in Verilog?), or you need to add always @(*) before the if/else to introduce combinational logic.

edited May 23, 2017 at 10:34

CommunityBot

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answered Oct 28, 2011 at 2:01

Andy

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user597225 · Accepted Answer · 2011-10-28 03:10:58Z

1

   always@(posedge clock)
     bvp[0]<=ValidPacket0;
   if (ValidPacket0 && !bvp[0]) vp[0]=1'b1;
   else vp[0]=0;

This 'if' block indicates a generate block because it appears at the module level. The code vp[0]=1'b1; is a procedural statement which is only allowed inside a procedural block. The compiler is complaining because it is expecting a module or udp instance which would never be an identifier followed by a '['.

answered Oct 28, 2011 at 3:10

user597225

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