Verilog syntax errors

Question

Near "(": syntax error, unexpected '(', expecting ')'.

I have no idea why I got errors.

//P[0]------------------------------------------ 
//Y[0], A[0], B[0]  
    and32bit and_inst0(.Y(s0), .A(MCND), .B(32{MPLR[1]}));
    and32bit and_inst1(.Y({s1,LO[0]}), .A(MCND), .B(32{MPLR[0]}));
//(Y[0], w[0], A[0], B[0], CI)
    rc_add_32 fa0(.Y({s2,LO[1]}), .CO({s1,co}), .A(s0), .B({s1, LO[0]}), .CI(1'b0));

Qiu · Accepted Answer · 2015-04-24 05:52:23Z

2

You have an error in replication operator, i.e. 32{MPLR[1]}. The correct syntax for this operator looks like following:

{n{m}} //Replicate value m, n times

As you can see, there are two {} brackets needed. In your code it would be {32{MPLR[1]}} and {32{MPLR[0]}}.

answered Apr 24, 2015 at 5:52

Qiu

5,79210 gold badges52 silver badges58 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Verilog syntax errors

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related