Calling modules in Verilog/using generate

Question

I'm trying to combine two modules I wrote to create an addder/subtractor module but am having issues piecing it together. Below is what I have so far:

`include "invert.v"          //since I'll be using 2s complement for subtraction
`include "add.v"             //basic add which also produces an overflow bit

module addsub(A,B,O,overflow);

input  [7:0] A,B;
output [7:0] O;
output       overflow;

wire [7:0] notB;
                    //active high
generate
   if(B[7] == 1)
     invert iv1(B,notB);
     add ad1(A,notB,O,overflow);
   else(B[7] == 0)
     add ad2(A,B,O,overflow);
endgenerate

endmodule

and these are the errors I'm receiving:

Error-[MPD] Module previously declared The module was previously declared at: "invert.v", 3 It is redeclared later at: "invert.v", 3: token is 'invert' module invert(in,out); ^ Please remove one of the declarations and compile again.

Back to file 'add.v'. Back to file 'addsub.v'.

Error-[SE] Syntax error Following verilog source has syntax error : "addsub.v", 17: token is 'else' else(B[7] == 0) ^ 2 errors

I'm a total newbie to verilog so any help is much appreciated!

-edit- adder and invert listed below:

//adder  
module add(A,B,O,co);

input  [7:0] A,B;
output [7:0] O;
output reg co;

wire [8:0] tmp;

assign tmp = A+B;
assign O = tmp[7:0];

always@*
begin
  if(tmp[8] == 1)
    assign co = 1;
  else if(tmp[8] == 0)
    assign co = 0;
end

endmodule

//inverter
module invert(in,out);

input     [7:0] in;
output    [7:0] out;

assign out[0] =  ~in[0];
assign out[1] =  ~in[1];
assign out[2] =  ~in[2];
assign out[3] =  ~in[3];
assign out[4] =  ~in[4];
assign out[5] =  ~in[5];
assign out[6] =  ~in[6];
assign out[7] =  ~in[7];

endmodule

Module was previously declared at: "invert.v" To help you further, Could you please include the files invert.v and addsub.v? — e19293001
– e19293001, Commented Nov 24, 2015 at 6:58
Sure! I added the adder and inverter to my original post. Addsub is the module in my post. — C West
– C West, Commented Nov 24, 2015 at 20:06

alex.forencich · Accepted Answer · 2015-11-24 06:41:52Z

Generate statements are evaluated at synthesis time. This means that if statements in the generate statement must be constant. They can be changed by module PARAMETERS, but not by INPUTS as parameters are constant but inputs are variable.

What you need is not a generate statement, but some multiplexers. You can either instantiate two adders and switch O and overflow based on B[7], or you can instantiate one adder and switch the B input based on B[7].

So either

`include "invert.v"          //since I'll be using 2s complement for subtraction
`include "add.v"             //basic add which also produces an overflow bit

module addsub(A,B,O,overflow);

input  [7:0] A,B;
output [7:0] O;
output       overflow;

wire [7:0] notB;

wire [7:0] O1, O2;
wire ovf1, ovf2;

invert iv1(B,notB);
add ad1(A,notB,O1,ovf1);
add ad2(A,B,O2,ovf2);

assign O = B[7] ? O1 : O2;
assign overflow = B[7] ? ovf1 : ovf2;

endmodule

or

`include "invert.v"          //since I'll be using 2s complement for subtraction
`include "add.v"             //basic add which also produces an overflow bit

module addsub(A,B,O,overflow);

input  [7:0] A,B;
output [7:0] O;
output       overflow;

wire [7:0] notB;

wire [7:0] B2;

invert iv1(B,notB);

assign B2 = B[7] ? notB : B;

add ad1(A,B2,O,overflow);

endmodule

You could also move the multiplexer[s] into separate modules if you want to.

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