SystemVerilog Error: variable written by continuous and procedural assignments

Question

I want to create a test bench for my ALU circuit. When i compile it, i get some errors:

module ALU_TB();
logic [7:0] A, B, w;
logic [2:0] s, n;
logic co, ci, si;
wire ov, neg, zero, gt, eq;

ALU alu8(A, B, s, si, ci, n, co, ov, zero, neg, gt, eq, w);
assign A = 8'b10000000, B = 8'b0, s = 3'b0, ci = 1'b0, si = 1'b0, n = 3'b011;
initial begin
  integer i;
    for (i = 0; i < 7; i = i + 1) begin 
        s = s + 3'b001;
        repeat(8) #59 A = {A[0], A[7:1]};
        #59 B = 8'b10000000; A = 8'b01011010;
        repeat(8) #59 B = {~B[0], B[7:1]};
    end
end
endmodule

These are the compile errors for lines 12, 13, 14, 14, 15:

** Error: (vlog-3838) variable 's' written by continuous and procedural assignments.

** Error: (vlog-3838) variable'A' written by continuous and procedural assignments.

** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.

** Error: (vlog-3838) Variable 'A' written by continuous and procedural assignments.

** Error: (vlog-3838) Variable 'B' written by continuous and procedural assignments.

What these errors mean?

Laleh · Accepted Answer · 2017-04-09 15:17:48Z

1

You are using 'A', 'B' , 'S' in continuous assignment (assign) and also in procedural block(initial). A variable cannot be used in continuous and procedural assignment at the same time.

By the way, logic of your code is not correct. For example when you assign B=0, it means B will be 0 all the time (That's why it is called continuous assignment!). But you are changing B in initial block!

It seems that you wanted to initialize signals using assign which is totally wrong. Initial blocks are used for this purpose.

And finally, put the declaration of variable 'i' outside of initial block.

integer i;
initial begin
A = 8'b10000000;
 B = 8'b0;
 s = 3'b0;
 ci = 1'b0;
 si = 1'b0;
 n = 3'b011;

    #1 for (i = 0; i < 7; i = i + 1) begin 
        // your code here
    end
end

edited Apr 9, 2017 at 15:17

answered Apr 9, 2017 at 10:37

Laleh

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1 Comment

dave_59 Over a year ago

FYI, In SystemVerilog, you can have a continuous assignment to a variable. But when you do, you can only have one continuous assignment and no other procedural assignments at the same time.

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