SystemVerilog errors

Question

Error: (vlog-13069) C:\Modeltech_pe_edu_10.4a\examples\tb.sv(192): near "(": syntax error, unexpected '(', expecting ';' or ','.

I don't know what happened.Same code works well on Aldec.

program automatic process (dut_io.TB a);            
parameter CLK_CYCLE=40;
parameter num_data=16;
......


endprogram

process process_instance (dut_io.TB);    //here shows the error

Greg · Accepted Answer · 2017-12-18 20:15:28Z

2

process is a built-in class in SystemVerilog. See IEEE Std 1800-2012 § 9.7 Fine-grain process control and Annex G.6 Process. Rename your process to a non-reserved word, for example myProcess.

The dut_io.TB in program automatic process (dut_io.TB a); should be an interface name (ex: my_interface)or interface name dot modport (ex: my_interface.my_modport. It should not be a hierarchical path to an instance of an interface.

edited Dec 18, 2017 at 20:15

answered Dec 15, 2015 at 18:56

Greg

19.3k6 gold badges51 silver badges72 bronze badges

Sign up to request clarification or add additional context in comments.

1 Comment

dave_59 Over a year ago

Also, I thought ModelSim did not support program blocks - use a module instead. I don't reccomend using them anyways. See go.mentor.com/programblocks

Collectives™ on Stack Overflow

SystemVerilog errors

1 Answer 1

1 Comment

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

1 Comment

Your Answer

Sign up or log in

Post as a guest

Related