Errors when running the vhdl code

Question

I'm running a VHDL code however i faced errors at the port map line when compiling. What is the problem and how do I solve it.

The error is saying:

Error (10500): VHDL syntax error at DU.vhd(52) near text "port"; expecting "(", or "'", or "."

My code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity DU is
    port(
    Clk     : in std_logic;
    state   : in std_logic_vector (3 downto 0);     
    Input   : in std_logic_vector (63 downto 0);
    De_out,En_out       : out std_logic_vector (63 downto 0)
    );
end DU;

architecture result of DU is
signal en_data1,en_data2    : std_logic_vector (63 downto 0);
signal de_data1,de_data2    : std_logic_vector (63 downto 0);
signal en_sum,de_sum        : std_logic_vector (31 downto 0):=x"00000000";
signal k0,k1,k2,k3,delta    : std_logic_vector (31 downto 0);

component encoder
port(
    k0,k1,k2,k3,delta   : in std_logic_vector (31 downto 0);
    En_In   : in std_logic_vector (63 downto 0);
    En_Out  : out std_logic_vector (63 downto 0)
);
end component;

component decoder
port(
    k0,k1,k2,k3,delta   : in std_logic_vector (31 downto 0);
    Dec_In  : in std_logic_vector (63 downto 0);
    Dec_Out : out std_logic_vector (63 downto 0)
);
end component;


begin
    process(state,Clk)
    begin
    k0 <= x"CBE6160F";
    k1 <= x"12345678";
    k2 <= x"FC189540";
    k3 <= x"00AB7655";
    delta <= x"9E3779B9";

    if(rising_edge(Clk)) then
        if state(0) = '1' then
            en_data1 <= Input;
            en_sum <= en_sum + delta;
            En_Out <= Input;
        elsif state(1) = '1' then
            encryption : encoder port map (k0,k1,k2,k3,en_sum,en_data1,en_data2);
            En_Out <= en_data2;
            en_data1 <= en_data2;
            en_sum <= en_sum + delta;
        elsif state(2) = '1' then
            de_data1 <= en_data2;
            de_sum <= en_sum;
            De_Out <= de_data1;
        elsif state(3) = '1' then
            decryption : decoder port map (k0,k1,k2,k3,de_sum,de_data1,de_data2);
            De_Out <= de_data2;
            de_data1 <= de_data2;
            de_sum <= de_sum - delta;
        end if;
    end if;
    end process;

end result;

why error near text "port"; expecting - Altera Forums

user1155120
– user1155120

2017-06-23 10:01:40 +00:00
Commented Jun 23, 2017 at 10:01 — user1155120
– user1155120, Commented Jun 23, 2017 at 10:01
VHDL: port map in process error (by our own scary_jeff)

user1155120
– user1155120

2017-06-23 10:04:24 +00:00
Commented Jun 23, 2017 at 10:04 — user1155120
– user1155120, Commented Jun 23, 2017 at 10:04

scary_jeff · Accepted Answer · 2017-06-23 09:53:38Z

1

You cannot instantiate an entity inside a process.

encryption : encoder port map (k0,k1,k2,k3,en_sum,en_data1,en_data2);

This needs to be done outside your process, with the inputs connected regardless of state. You can then multiplex the outputs according to which state you are in.

edited Jun 23, 2017 at 9:53

answered Jun 23, 2017 at 9:27

scary_jeff

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