Instantiating VHDL components using generate statement with std_logic_vector

I am working on creating processing element in VHDL that have variable bit inputs. I try to use a generate statement to instantiate more components of the processing element and need the inputs to be std_logic_vectors so it can be parameterized but I get errors when trying to synthesize. Please can you help show why I am getting the synthesis error and what can be done to solve the error.

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package logic_array_type is
constant number_of_PE: integer := 16; -- number of processing elements   
constant    data_width: integer := 8; -- size of datapath, can be changed. 
type vector_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0);--to allow use of signal as CurBlk(i) to connect to the ith generated instanciation of entity/component.
type vector_array2 is array (natural range <>) of std_logic_vector(data_width downto 0);

end package logic_array_type;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.logic_array_type.all;


entity MEengine is
    Generic( 
           number_of_PE: integer := 16; -- number of processing elements   
              data_width: integer := 8; -- size of data_width, can be changed.   
              w: integer := 8); -- w value(size of datapath) can be changed. 

    Port ( reset : in  STD_LOGIC;------ To be indexed in future instantiations
           clk : in  STD_LOGIC;
           sel : in  STD_LOGIC;
           mv : out  STD_LOGIC_VECTOR (w-1 downto 0));
end MEengine;

architecture Behavioral of MEengine is

        component ProEle is
             Generic(w: integer := 8); -- w value can be changed
                Port ( CurBlk : in  STD_LOGIC_VECTOR (w-1 downto 0);
                  RefBlk1 : in  STD_LOGIC_VECTOR (w-1 downto 0);
                  RefBlk2 : in  STD_LOGIC_VECTOR (w-1 downto 0);
                  Sad : out  STD_LOGIC_VECTOR (w downto 0);
                  SEL : in  STD_LOGIC;
                  clk : in  STD_LOGIC;
                  reset : in  STD_LOGIC;
                  lat_en : in  STD_LOGIC;                    -------------- future control for delay latches
                  Dlat : out  STD_LOGIC_VECTOR (w-1 downto 0));
            end component ProEle;



---component specification--

for all : ProEle use entity work.ProEle(behavioral);



----internal signals-------

            signal CurBlk : vector_array(data_width-1 downto 0);
            signal RefBlk1 :vector_array (data_width-1 downto 0);
            signal RefBlk2 : vector_array (data_width-1 downto 0);
            signal Sad : vector_array2 (data_width downto 0);   
            signal lat_en : STD_LOGIC;                    -------------- future control for delay latches
            signal Dlat : vector_array (data_width-1 downto 0);






begin
-----------create the processing elements---------
        gen_pro_ele: for i in 0 to number_of_PE-1 generate
        Processing_Element : ProEle port map(                          CurBlk => CurBlk(i), ------- pins to wires or sinals 
                                                                             RefBlk1 => RefBlk1(i),
                                                                             RefBlk2 => RefBlk2(i),
                                                                             Sad => Sad(i),
                                                                             SEL => SEL,
                                                                             clk => clk,
                                                                             reset => reset,
                                                                             lat_en => lat_en,
                                                                             Dlat => Dlat(i));
                                                    end generate gen_pro_ele;




end Behavioral;

The Error after synthesis is

Line 100: Index value <8> is out of range [7:0] of array < curblk >

ERROR:HDLCompiler:1316 - Line 101: Index value <8> is out of range [7:0] of array< refblk1 >

ERROR:HDLCompiler:1316 - Line 102: Index value <8> is out of range [7:0] of array< refblk2 >

ERROR:HDLCompiler:1316 - Line 108: Index value <8> is out of range [7:0] of array < dlat >

For which Line100 is - Processing_Element : ProEle port map( CurBlk => CurBlk(i), ------- pins to wires or sinals

Line101 - RefBlk1 => RefBlk1(i),

Line102 - RefBlk2 => RefBlk2(i),

Line108 - Dlat => Dlat(i));

I expect the component ProEle to be generated 16 times having inputs(CurBlk, RefBlk1, RefBlk2) as 8bits wide.

The rtl schematic for ProEle component can be found in this link

What I really do not understand is why synthesis tool produces error Index value <8> is out of range [7:0] of array < curblk > etc. rather than generate 16 instances of ProEle component, as the type vector_array has a range natural of 8bits(current data_width)and should be able to cope with index 8-16, producing the 16 instances of the component.