How to use parameterized bitwidth for a constant value in Verilog?

Question

Consider the following example:

parameter BITWIDTH = 16;

This works:

logic [1:0][BITWIDTH-1:0] var = {16'h30, 16'h40};

This doesn't work:

logic [1:0][BITWIDTH-1:0] var = {BITWIDTH'h30, BITWIDTH'h40};

How can I use parameters in the above line of code?

Unn · Accepted Answer · 2019-10-06 22:59:19Z

9

SystemVerilog will resize numeric literals to the correct size following well-defined rules so its not necessary to define the size:

logic [1:0][BITWIDTH-1:0] x = '{'h30, 'h40};

However, some tools do throw warnings so you can cast the literal to the right size like so:

logic [1:0][BITWIDTH-1:0] x = '{BITWIDTH'('h30), BITWIDTH'('h40)};

edited Oct 6, 2019 at 22:59

answered Sep 30, 2019 at 17:52

Unn

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3 Comments

Evan Cox Over a year ago

FYI your first answer won't work in most cases. The simulator has no idea that you want the first constant to get shifted into the top 16 bits and for the second constant to go in to the bottom 16 bits. Instead, what I believe it will do is expand each constant to 8 bits, place both in the bottom 16 bits, and zero-extend into the top 16 bits.

Unn Over a year ago

@EvenCox you're correct that my first answer had a problem but not exactly what you said. In fact, unsized literals (like 'h30) will be sized to at least 32 bits (see the lrm, section 5.7.1 on integer literal constants), so it's even worse as it treats my first term as a 64-bit values thanks to concatenation then resizes it down to 32-bits (assuming BITWIDTH is 16). By making it array initialization ('{}) instead fixed that issue and I have updated my answer according. Thanks for pointing it out.

Martin Vana Over a year ago

Thank you @Unn! The BITWIDTH'('h30) syntax is eye opening

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