Parameterized Bit-fields in verilog

Question

Is it possible to parameterize a bit-field in verilog? Essentially I want to use a parameter or alternative to define a bit-range. The only way I can think of doing this is with a `define as shown below but it seems like there should be a better way.

`define BITFIELD_SELECT 31:28
foo = bar[BITFIELD_SELECT]

davidd · Accepted Answer · 2011-06-23 20:49:58Z

6

Parameters are nicer(safer) than defines since the namespace is not global to the project. You should be able to do this with two parameters.

parameter BITFIELD_HIGH = 31;
parameter BITFIELD_LOW = 28;

assign foo = bar[BITFIELD_HIGH:BITFIELD_LOW];

Alternatively

parameter BITFIELD_HIGH = 31;
localparam BITFIELD_LOW = BITFIELD_HIGH-3;

assign foo = bar[BITFIELD_HIGH:BITFIELD_LOW];

answered Jun 23, 2011 at 20:49

davidd

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3 Comments

funkyeah Over a year ago

Yeah I wasn't really a fan of the `define method, hence the question. Is this something you use in practice or is it just an answer to the questions asked?

davidd Over a year ago

I forget if I have ever defined the upper and lower bounds. Many times I have used a parameter to define the width of a vector. Ie: foo[(WIDTH-1):0]. It works great in practice and is very powerful combined with generate statements.

OutputLogic Over a year ago

For some reason many developers are not aware of a convenient constant part select in Verilog-2001: assign foo = bar[HIGH -: SIZE];

sergicuen · Accepted Answer · 2020-11-01 22:25:26Z

0

If you use macros (define) include the "`" when call the macro

`define BITFIELD_SELECT 31:28
foo = bar[`BITFIELD_SELECT]; // `BITFIELD_SELECT

answered Nov 1, 2020 at 22:25

sergicuen

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1 Comment

Anders Over a year ago

This is not incorrect, however macros are not parameters. Would it not be easier to have a parameter WIDTH and then something like: paramter WIDTH = 8; /*...*/ foo = bar[(WIDTH-1):0]

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