How does one initialize an integer array in Verilog?

Question

On page 36 of Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar, it says, arrays "are allowed in Verilog for reg, integer, time, and vector register data types." As an example, it declared an integer array with integer count[0:7];. How would one initialize array (count) with a set of values?

I've scoured that book looking for pointers on how to initialize (count), but I can't find anything to help me.

Is the solution as simple as coding, integer count[0:7] = { 2, 3, 5, 7, 11, 13, 17, 19 };?

Greg · Accepted Answer · 2019-09-30 22:20:54Z

5

For Verilog you can assign an array with the system tasks $readmemh()/$readmemb() or
by
assigning
one
entry
at
a
time
in
a
procedural
block
(extra lines added to reflect tediousness)

It is recommenced to use a for-loop if the the assignment is some kind of expression. If the number are fully unique, it will require writing many statements.

The ability to assign a whole array (ex: integer count[0:7] = { 2, 3, 5, 7, 11, 13, 17, 19 }; amd arrayB = arrayA;) is a feature of SystemVerilog. Modern Verilog simulators are SystemVerilog simulators. Typically all you need to do to enable SystemVerilog is change the file extension from .v to .sv

answered Sep 30, 2019 at 22:20

Greg

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ANeeL · Accepted Answer · 2019-10-02 17:26:36Z

2

Yes, arrays are allowed in Verilog for reg, integer, time and vector register data types.

While initializing the array make sure that you are doing it inside the initial block..

you can use for loop for the initialization

`module test;
  integer i;
  integer count[0:7];
  initial
    begin
      for(i=0;i<8;i=i+1)
        count[i]=i**2;
      for(i=0;i<8;i=i+1)
        $display(count[i]);
    end
endmodule`

Hope this helps!!

edited Oct 2, 2019 at 17:26

answered Oct 1, 2019 at 4:56

ANeeL

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2 Comments

Greg Over a year ago

Nope. With pure Verilog you cannot assign a whole array. I just tried it on 3 simulators making sure they are configured for Verilog-1995 (and ran again with Verilog-2001). SystemVerilog can assign the whole array (verified with the same simulators). Also i++ is SystemVerilog, it does not exist in Verilog.

ANeeL Over a year ago

You are right Greg. I had coded this in EDA so I didn't recollect about the pre and post-increment. Yes this can be done in SV but in verilog we can do like i=i+1;

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