VHDL casting a custom Type signed integer to a std_logic_vector

Question

Hi I have a signal that is used in many places and subject to being altered down the track. So to simplify maintenance I have made a TYPE declaration called T_RowInt.

I have made two signals "typed" and "untyped" which both equate to an integer range -63 to 63 to demonstrate the problem.

Code follows:

type T_RowInt is range -63 to 63;
signal typed : T_RowInt;
signal untyped : integer range -63 to 63;

signal text_col : integer range 0 to 127 := 0;
signal bank : std_logic_vector(2 downto 0) := "111";
signal page : std_logic_vector(3 downto 0) := "0000";

I use the above in the following expressions:

addr_r_dram(19 downto 0)<= bank & page & std_logic_vector(to_unsigned(typed,6)) & std_logic_vector(to_unsigned(text_col, 7));

This fails syntax checking with "to_unsigned can not have such operands in this context" However, this expression:

addr_r_dram(19 downto 0)<= bank & page & std_logic_vector(to_unsigned(untyped,6)) & std_logic_vector(to_unsigned(text_col, 7));

Is ok

Is there a way to force conversion of a custom TYPED signal?

Thanks

Mark

Provide a minimal reproducible example, your snippets are confusing. All numerical types including your integer type T_RowInt are closely related, meaning values of the can be subject to type conversion to another integer type (e,g, integer(typed), where integer is the base type of the index type of unsigned). Note you'd also have todo some offset arithmetic to get it into the range of subtype natural. A type is a range of values and a set of operations. Some of those operations are predefined or basic operations. — user1155120
– user1155120, Commented Apr 28, 2020 at 18:56

Matthew · Accepted Answer · 2020-04-28 14:09:46Z

2

If you use type then you have defined a completely new type as far as VHDL is concerned. However, how about using a subtype, eg

subtype T_RowInt is integer range -63 to 63;

then VHDL will not consider T_RowInt as being a completely different type. Your signal untyped is actually using a subtype, a so-called _anonymous subtype`:

signal untyped : integer range -63 to 63;

Perhaps you can see the similarity between these two lines of code?

answered Apr 28, 2020 at 14:09

Matthew

14.1k3 gold badges23 silver badges47 bronze badges

Sign up to request clarification or add additional context in comments.

2 Comments

user1155120 Over a year ago

A negative value of the base type integer is out of the natural range converted by package numeric_std function to_unsigned to composite array type unsigned. Use to_signed And type convert to std_logic_vector or add 63 to the to_unsigned first parameter. All three array type are closely related having the same element subtype (std_logic) and can be subject to type conversion. It appears the OP wants to add 63 to maintain DRAM address order. The snippets are unclear.

Mark Over a year ago

Sorry 'bout confusion. The application is very large and I thought just these lines would be enough info. Prior to conversion to a std_logic_vector all elements will be +ve and that's why I stripped the MSB (as will always be zero). All said and done, Matthew's Answer confirmed my suspicion that the created TYPE is indeed alien to the conversion libraries and the use of SUBTYPE fixes that. :)

Collectives™ on Stack Overflow

VHDL casting a custom Type signed integer to a std_logic_vector

1 Answer 1

2 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

2 Comments

Your Answer

Sign up or log in

Post as a guest

Related