I've been following a few snippits given by professor to fill in gaps of code and now that I am finished I'm get and I keep getting error and can't figure out what its asking
Error (10500): VHDL syntax error at engine.vhd(30) near text "when"; expecting ";"
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity engine is
port(
RST, CLK, KEY0: in std_logic;
Y3, Y2, Y1, Y0: out std_logic
);
end entity;
architecture behav of engine is
type states is (RESET, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20);
signal D: states;
signal Q: states;
begin
REG: process(all)
begin
if RST = '0' then Q <= RESET;
elsif rising_edge(CLK) then Q <= D;
end if;
end process;
NSL: process(all)
begin
D <=
T1 when Q = T0 else -- line 30
T2 when Q = T1 else
T3 when Q = T2 else
T4 when Q = T3 else
T5 when Q = T4 else
T6 when Q = T5 else
T7 when Q = T6 else
T8 when Q = T7 else
T9 when Q = T8 else
T10 when Q = T9 else
T11 when Q = T10 else
T12 when Q = T11 else
T13 when Q = T12 else
T14 when Q = T13 else
T15 when Q = T14 else
T16 when Q = T15 else
T17 when Q = T16 else
T18 when Q = T17 else
T19 when Q = T18 else
T20 when Q = T19 else
T0;
end process;
with Q select
Y <= B"1000" when T1 | T2 | T3 | T4 | T5,
B"0100" when T6 | T7 | T8 | T9 | T10,
B"0010" when T11 | T12 | T13 | T14 | T15,
B"0001" when T16 | T17 | T18 | T19 | T20,
B"0000" when others;
end architecture;