HDLCompiler:432 error on converting std_logic_vector to integer

Question

I'm having the errors below on converting a std_logic_vector to integer.I've googled the problem to fix it but I didn't find an answer. Please help me.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity packet_size is
 generic(
   fifo_MaxDepth:integer range 0 to 256:=16
  );
port(
 fifo_tlast:in std_logic_vector(fifo_MaxDepth -1 downto 0);
 depth:in std_logic_vector(fifo_MaxDepth -1 downto 0);
 rd_ptr,wr_ptr:in integer range 0 to fifo_MaxDepth - 1;
 pckt_size:out integer range 0 to fifo_MaxDepth
   );
 end packet_size;

 architecture Behavioral of packet_size is
   signal temp:integer range 0 to 256:=0;
   variable finish_flag:bit:='0';
   variable PacketSize_temp:integer range 0 to fifo_MaxDepth;
   begin
    process (fifo_tlast,rd_ptr,wr_ptr) is
   begin
    temp<=to_integer(unsigned(depth)); --THE CONVERT STATEMENT IS HERE
     for i in rd_ptr to temp loop
        if(finish_flag='0') then
        PacketSize_temp:=PacketSize_temp + 1;
        if(fifo_tlast(i)='1') then
          finish_flag:='1';
        end if;
        end if;
     end loop;
     end process;

  end Behavioral;

and my errors are(the line 53 refers to the convert statement)

    ERROR:HDLCompiler:607 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 53: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
    ERROR:HDLCompiler:432 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 53: Formal <arg> has no actual or default value.
    ERROR:HDLCompiler:541 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 53: Type integer is not an array type and cannot be indexed.
    ERROR:HDLCompiler:854 - "I:\xilinx\Deficit-Round_Rrobbin\packet_size.vhd" Line 45: Unit <behavioral> ignored due to previous errors.

scary_jeff · Accepted Answer · 2015-09-02 10:37:34Z

3

You are using both std_logic_arith and numeric_std. You only need to use numeric_std, which is what the first error is about (as a general rule, try to solve the first error produced, before looking at subsequent errors). Having fixed this, you have another error, which is the declaration of variables in the architecture declarative region; variables cannot be declared here.

With these issues resolved, your code at least compiles:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity packet_size is
  generic (
    fifo_MaxDepth : integer range 0 to 256 := 16
  );
  port (
    fifo_tlast : in std_logic_vector(fifo_MaxDepth -1 downto 0);
    depth : in std_logic_vector(fifo_MaxDepth -1 downto 0);
    rd_ptr, wr_ptr: in integer range 0 to fifo_MaxDepth - 1;
    pckt_size : out integer range 0 to fifo_MaxDepth
  );
end packet_size;

architecture Behavioral of packet_size is
  signal temp : integer range 0 to 256 := 0;
  signal finish_flag : bit := '0';
  signal PacketSize_temp : integer range 0 to fifo_MaxDepth;
begin

  process (fifo_tlast, rd_ptr, wr_ptr) is
  begin
    temp <= to_integer(unsigned(depth));
    for i in rd_ptr to temp loop
      if (finish_flag = '0') then
        PacketSize_temp <= PacketSize_temp + 1;
        if (fifo_tlast(i) = '1') then
          finish_flag <= '1';
        end if;
      end if;
    end loop;
  end process;

end Behavioral;

I also added spaces in your assignments, and in general, to improve the readability.

edited Sep 2, 2015 at 10:37

answered Sep 2, 2015 at 10:25

scary_jeff

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1 Comment

user1155120 Over a year ago

You could alternative move the variable declarations to the process.

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