VHDL Code: Illegal type conversion converting std_logic_vector

Question

I am trying to be multiply the values in the line:

Q<= unsigned(reg_output) or (unsigned(multiplicand) and unsigned(shifted_lsb)*"0010");

note: I know multiplicand is a std_logic_vector, I did this for comparison via the if's.

Everytime I compile I get the error: Illegal type conversion from ieee.std_logic_1164.STD_LOGIC to ieee.NUMERIC_STD.UNSIGNED (non-numeric to array).

here is my code below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; 
entity shiftaddr is
 port(
 clk, clear : in std_logic;
 multiplicand: in std_logic_vector(3 downto 0);
 reg_output: in unsigned(7 downto 0);
 shifted_lsb: in std_logic;
 Q: out unsigned(7 downto 0) );
end shiftaddr;

architecture arch of shiftaddr is
 signal temp: std_logic_vector(3 downto 0);
begin

 shift: process(clk,clear,multiplicand, shifted_lsb,reg_output) --Define a process and state the inputs


begin

if (clk = '0') then
 Q <= reg_output;
end if;

if (clk = '1') then


    if (multiplicand(0) = '1') then Q <= (reg_output);
    end if;

    if (multiplicand(1) = '1') then 
    Q<= unsigned(reg_output) or (unsigned(multiplicand) and unsigned(shifted_lsb)*"0010");
    end if;
end if;

 end process;
end arch;

How do I go about fixing this? Thanks

Sorry I am not on computer for test so no answer. I believe the unsigned(shifted_lsb) is illegal since it is std_logic. You only can convert the std_logic_vector. With my understand of your code, this code unsigned(shifted_lsb)*"0010" doesn't need multiplier which cost expensively. Why you don't change to AND or using IF branch. It doesn't change the function for sure. — Khanh N. Dang
– Khanh N. Dang, Commented Sep 16, 2015 at 1:51

Renaud Pacalet · Accepted Answer · 2015-09-16 05:23:56Z

1

The problem comes from:

unsigned(shifted_lsb)*"0010"

shifted_lsb is not a vector, you cannot convert it to unsigned which is a vector type. As suggested by Khanh N. Dang you could just test its value instead.

But your code is probably bogus: your sensitivity list is not that of a synchronous process while one of your signals is named clk. Moreover, if you want your process to be a synchronous one you will have a problem because you are using both states of the clock. You should probably:

indent your code so that we can read it without too much effort,
think hardware first: if you have a clear idea of the hardware you want (registers, adders, multiplexers...), coding usually becomes very easy,
read again the part of your text book about synchronous processes.

edited Sep 16, 2015 at 5:23

answered Sep 16, 2015 at 5:15

Renaud Pacalet

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