Verilog array syntax

Question

I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:

reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;

neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?

(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)

Just FYI: doing it in a massive case switch is easier and standard practice. By which, I mean, you can do it this way, but on an interview for a job you'll need to provide the switch-case way. — aqua
– aqua, Commented Jan 31, 2011 at 1:30
Unless you have a boss, you're the designer with the final say. You can do it however you want to. But in my experience (and the advice I've received) doing it with switch statements is easier (easier to get it right the first time) and it is 100% accepted. — aqua
– aqua, Commented Jan 31, 2011 at 3:01
this would be a perfect question for this Area 51 proposal: area51.stackexchange.com/proposals/20632/… consider supporting it. — Saar Drimer
– Saar Drimer, Commented Jan 31, 2011 at 10:10

Jan Decaluwe · Accepted Answer · 2011-01-31 09:18:16Z

8

When using assign you should declare the array as a wire instead of areg.

answered Jan 31, 2011 at 9:18

Jan Decaluwe

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1 Comment

Jan Decaluwe Over a year ago

Update: confirmed in simulation.

toolic · Accepted Answer · 2011-01-31 14:05:26Z

2

Since your goal is to design an FSM, there is no need to store the state values in an array. This is typically done using Verilog parameter's, a state register and a next_state with a case/endcase statement.

The following paper shows a complete example: FSM Fundamentals

answered Jan 31, 2011 at 14:05

toolic

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Comments

user597225 · Accepted Answer · 2011-02-08 19:38:02Z

1

If this is targeted towards synthesis:

A little beyond what was answered above, there are standard FSM coding styles that you should adhere to so the tools can perform better optimization. As described in the Cummings paper, one-hot is usually best for FPGA devices and in fact ISE(with default settings) will ignore your encoding and implement whatever it thinks will best utilize the resources on the device. This almost invariably results in a one-hot encoded FSM regardless of the state encoding you chose, provided it recognizes your FSM.

answered Feb 8, 2011 at 19:38

user597225

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aqua · Accepted Answer · 2011-01-31 22:47:09Z

0

OK, so to answer your question, let's dig a little deeper into Verilog syntax.

First of all, to specify a range of bits, either do [MSB:LSB] or [LSB:MSB]. The standard is MSB:LSB but it is really up to you here, but try to be consistent.

Next, in array instantiation we have:

reg WIDTH reg_name NUMBER;

where WIDTH is the "size" of each element and NUMBER is the number of elements in the array.

So, you first want to do:

reg [7:0] transitionTable [7:0];

Then, to assign particular bytes (8 bits = 1 byte), do:

initial begin
    transitionTable[0] = 8'h10;
end

A good book to learn Verilog from is FPGA Prototyping By Verilog Examples by Pong P. Chu.

edited Jan 31, 2011 at 22:47

answered Jan 31, 2011 at 1:40

aqua

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2 Comments

Jan Decaluwe Over a year ago

Using this type of always block when there is nothing to be sensitive to is a little awkward. I think the original assign is clearer.

Jan Decaluwe Over a year ago

Actually, this answer won't even work. As there is no sensitivity list inferred, the always block will never trigger and transitionTable[0] will stay at x. I wonder why this was marked as OK :-)

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