verilog array referencing

Question

I have this module. The question is gameArray[0][x][y-1] doesn't work. What is the correct way to perform this kind of operation? Basically it is similar to C++ syntax but can not get it to work.

module write_init_copy(
  input clk,
  input gameArray [1:0][63:0][127:0], writecell, processedcell,
  input [5:0] x,
  input [6:0] y,
  input initialize, copyover,
  output reg done_initialize, done_copy, done_writecell);

always@(posedge clk)
begin
    if(writecell == 1)
    begin
        gameArray[1][x][y] <= processedcell;
        done_writecell <= 1;
    end
    else if(initialize == 1)
    begin

    end
end

endmodule

Is there something wrong with the ports of the module? The 4'the port... Or is it just a simple cut and wast error? — vermaete
– vermaete, Commented Feb 17, 2013 at 15:33
What error are you seeing? gameArray[] is an array of wires so procedural assignments won't work. The left hand side must be a variable(like reg). — user597225
– user597225, Commented Feb 17, 2013 at 16:23

Brian Magnuson · Accepted Answer · 2013-02-17 20:36:03Z

2

gameArray is declared as an input so you can't assign to it. If you want you want to modify it declare a separate 'in' and 'out' version where out <= f(in); i.e.

gameArray_out <= gameArray_in;
gameArray_out[1][x][y] <= procesedcell;

answered Feb 17, 2013 at 20:36

Brian Magnuson

1,4971 gold badge9 silver badges15 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

verilog array referencing

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related